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Distributed prefetch-buffer/cache design for high performance memory systems

T. Alexander, G. Kedem
Proceedings. Second International Symposium on High-Performance Computer Architecture  
A novel prediction and prefetching technique is combined with a distributed c ache architecture to build a high performance memory system.  ...  We present a high performance memory system architecture that overcomes the growing speed disparity between high performance microprocessors and current generation DRAMs.  ...  The authors thank Sanjay Vishin of Sun Microsystems for his help in setting up the tracing environment.  ... 
doi:10.1109/hpca.1996.501191 dblp:conf/hpca/AlexanderK96 fatcat:oqlbmnoconf3tfw4gg64kxrcju

Page 275 of IEEE Transactions on Computers Vol. 52, Issue 3 [page]

2003 IEEE Transactions on Computers  
Kedem, “Distributed Prefetch-Buffer/Cache Design for High Performance Memory Systems,” Proc. Second Int'l Symp. High-Performance Computer Architecture, Feb. 1996 {2} M. Annavaram, J. Patel, and E.  ...  Vranesic, “Memory-System Design Considerations for Dynamically-Scheduled Processors,” Proc, 24th Ann. Int'l Symp. Computer Architecture, June 1997 [17] K. Farkas and N.  ... 

MOBILE CONTENT DELIVERY IN INFORMATION-CENTRIC NETWORK Mobile Content Delivery in Information-Centric Network

Feixiong Zhang, Yanyong Zhang, Dipankar Raychaudhuri, Feixiong Zhang, Yanyong Zhang, Dipankar Raychaudhuri, Na-Garaja, Rich Howard, Yi Hu, Kai Su, Shreyasee Mukherjee, Shweta Sagari (+4 others)
unpublished
Nowadays, the Internet usage is shifting towards information distribution and retrieval, with mobile data access becoming the norm.  ...  buffered at the AP's prefetch buffer.  ...  The implementation uses Apache MINA as the network socket library to develop high performance network application, and utilizes BerkeleyDB to provide both in-memory and on-disk storage for GUID bindings  ... 
fatcat:vcklxjky7ffsrn5rk7erkvljle