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Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection

P. Kiss, J. Silva, A. Wiesbauer, Tao Sun, Un-Ku Moon, J.T. Stonick, G.C. Temes
2000 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
The first part of this two-part paper, published separately, discusses the quantization noise leakage problem caused in cascaded delta-sigma (MASH) analog-to-digital converters (ADC's) by the imperfections  ...  This paper describes the correction process, as well as some efficient structures for implementing it, and demonstrates the effectiveness of the technique by describing three design examples.  ...  His research interest has been in the area of analog and mixed analog-digital integrated circuits.  ... 
doi:10.1109/82.850422 fatcat:32ejguqcibfndadbb7g5lwahtq

Adaptive digital correction of analog errors in MASH ADCs. I. Off-line and blind on-line calibration

G. Cauwenberghs, G.C. Temes
2000 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
for digital correction of such analog imperfections, as well as gain and spectral distortion in the signal transfer function.  ...  Cascaded delta-sigma (MASH) modulators for higher order oversampled analog-to-digital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise  ...  CONCLUSION We have presented a simple calibration technique for adaptive digital correction of multiple quantization delta-sigma modulators.  ... 
doi:10.1109/82.850421 fatcat:taswo6d7ybax3crnsafcs4suqm

Highly Linear 2.5-V CMOS>tex<$Sigma Delta $>/textex<$hboxADSL+$>/tex<

R. delRio, J.M. delaRosa, B. Perez-Verdu, M. Delgado-Restituto, R. Dominguez-Castro, F. Medeiro, A. Rodriguez-Vazquez
2004 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
We present a 90-dB spurious-free dynamic range sigma-delta modulator (61M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate.  ...  It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-m CMOS process with metal-insulator-metal capacitors.  ...  ACKNOWLEDGMENT The authors would like to thank J. Ramos, J. Ceballos, and J. M. Mora for their valuable design and support, as well as S. Escalera and J. M.  ... 
doi:10.1109/tcsi.2003.821308 fatcat:e3z4pgfgsjbkdko6l5wnjhkvaq

The Philosophy of PCM

B.M. Oliver, J.R. Pierce, C.E. Shannon
1948 Proceedings of the IRE  
Oversampling in conjunction with quantization noise shaping and digital filtering are the key concepts in sigma-delta converters, although oversampling can be used with any ADC architecture.  ...  INTRODUCTION You don't have to deal with ADCs or DACs for long before running across this often quoted formula for the theoretical signal-tonoise ratio (SNR) of a converter.  ...  Also for communications applications, the AD9446 16-bit, 100 MSPS ADC is optimized for high SNR (84 dB), dissipates 2.8 W, and is also designed on a BiCMOS process.  ... 
doi:10.1109/jrproc.1948.231941 fatcat:n5mzm7dp45cojmrmzpanr5zv2y

A 81-dB Dynamic Range 16-MHz Bandwidth $\Delta\Sigma$ Modulator Using Background Calibration

Su-Hao Wu, Jieh-Tsorng Wu
2013 IEEE Journal of Solid-State Circuits  
Two different types of digital calibrations are used. We first employ the integrator leakage calibration to correct the poles of the integrators.  ...  A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology.  ...  ACKNOWLEDGMENT The authors would like to thank Taiwan Semiconductor Manufacturing Company (TSMC), Hsin-Chu, Taiwan, for chip fabrication under the TSMC University Shuttle Program.  ... 
doi:10.1109/jssc.2013.2264137 fatcat:n7tv2ncslngjpb557dmr7ykypu

2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26

2018 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
., see 2723-2736 , VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957  ...  Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J  ...  ., +, TVLSI May 2018 933-944 A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.  ... 
doi:10.1109/tvlsi.2019.2892312 fatcat:rxiz5duc6jhdzjo4ybcxdajtbq

Incremental Delta-Sigma Structures for DC Measurement: an Overview

Janos Markus, Philippe Deval, Vincent Quiquempoix, Jose Silva, Gabor C. Temes
2006 IEEE Custom Integrated Circuits Conference 2006  
Equations are derived for the estimation of the required number of cycles for a given resolution and architecture.  ...  In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (∆Σ) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described.  ...  INTRODUCTION Delta-Sigma (∆Σ) analog-to-digital converters are widely used in telecommunication and multimedia applications.  ... 
doi:10.1109/cicc.2006.320960 dblp:conf/cicc/MarkusDQST06 fatcat:k3fhqg74dzdyjjdypuvhbwzy5y

A Background Calibration Technique Based on Limit Cycles for Reconfigurable Sigma Delta Modulators

Ketan J. Pol, Sotir Ouzounov, Hans Hegt, Arthur H. M. van Roermund
2015 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
ACKNOWLEDGMENT This work is supported by STW and Philips Research, Eindhoven.  ...  It consists of an on-chip continuous time current input sigma delta ADC and an off-chip Sinc 3 filter.  ...  Our calibration technique is targeted primarily for reconfigurable SDMs. Sigma Delta Modulators (SDMs) are typically favored as reconfigurable ADCs. There are multiple reasons for this choice.  ... 
doi:10.1109/jetcas.2015.2502159 fatcat:6nhymmlrozhrhfdqhu2s45f7uu

Theory and Applications of Incremental$Delta Sigma $Converters

J. Markus, J. Silva, G.C. Temes
2004 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
The conventional delta-sigma (16) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset.  ...  The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the 16 converter, yet is capable of offset-free and accurate conversion.  ...  ACKNOWLEDGMENT The authors would like to thank Prof. I. Kollár for his useful comments.  ... 
doi:10.1109/tcsi.2004.826202 fatcat:mzhlhvzxhndkfeietvirg27j3e

A/D and D/A Conversion Architectures and Techniques [chapter]

Sameer Sonkusale, Takis Zourntos
2005 Encyclopedia of RF and Microwave Engineering  
Most of the digital schemes employ techniques to correct for errors by measuring code error transitions in the ADC transfer characteristics.  ...  This technique, proposed in Refs. 35 and 44, adaptively corrects for the residue errors in the pipeline with the use of a slow high-resolution ADC (typically a S À D ADC) for calibration.  ... 
doi:10.1002/0471654507.eme079 fatcat:ltl32w64hnfundph4a2ea6pq3m

Digital techniques for improved ΔΣ data conversion

J. Silva, X. Wang, P. Kiss, U. Moon, G.C. Temes
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)  
The first one corrects adaptively for mismatch errors in a MASH ADC, while the other acquires and then corrects for the nonlinearity of the intemal multibit DAC used in the ADC.  ...  Two digital techniques are described in this tutorial, both aimed at improving the accuracy of delta-sigma data converters.  ...  Acknowledgments The authors wish to thank A. Wiesbauer  ... 
doi:10.1109/cicc.2002.1012794 fatcat:n7p2d6jer5b2vaxee7ikijcjiu

Bandpass Delta-Sigma Converters in IF Receivers [chapter]

Armond Hairapetian
2001 Analog Circuit Design  
It also represents four of the five quality indicators named above: robustness, efficiency (low-power), accuracy (the highly-digitized receiver architecture requires a high resolution ADC) and flexibility  ...  The battery symbolizes the limited amount of energy available in mobile devices and therefore the high efficiency required from all its building blocks.  ...  Sigma Delta modulators trade amplitude resolution for time resolution, by using over-sampling in combination with noise shaping.  ... 
doi:10.1007/978-1-4613-1443-1_10 fatcat:cg34vk7z65cgleckvjw5lbhiqe

Look-Ahead Sigma-Delta Modulation [chapter]

Erwin Janssen, Arthur van Roermund
2011 Look-Ahead Based Sigma-Delta Modulation  
A Sigma-Delta DAC is the combination of a DD converter and a high-speed few-bit DAC. In fig. 2 .6 the complete Sigma-Delta DAC structure is shown.  ...  The feedback DAC performs the inverse function of the ADC (quantizer) and converts the n-bit digital code to an analog voltage or current, closing the Sigma-Delta loop.  ...  Derivation, implementation, and performance evaluation of the Pruned Tree SDM for SA-CD. • Comparison of all the major look-ahead sigma-delta modulation techniques, resulting in a clear motivation for  ... 
doi:10.1007/978-94-007-1387-1_5 fatcat:xhas4ns4cbffrac2ocztra4dam

Suppression of delta-sigma DAC quantisation noise by bandwidth adaptation

Jørgen Andreas Michaelsen, Dag T. Wisland
2007 Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07  
Unfortunately, the output from the MASH arrangement is inherently multibit, and thus incurs an increased complexity in the D/A module-either by requiring preprocessing of the multibit signal or by requiring  ...  In an arrangement dubbed MASH [6] , ∆Σ modulators are cascaded accompanied by error cancellation logic in order to eliminate the quantisation error from all but the last modulator.  ...  the power spectrum X = X .ˆ2; 51 % scale since we only use one side of the spectrum , % everything except dc and nyquist needs doubling X(2: end -1) = X(2: end -1) * 2; % make index to frequency map  ... 
doi:10.1145/1284480.1284493 dblp:conf/sbcci/MichaelsenW07 fatcat:v5oft3jaiff2lbkv5prvfjwjzi

Wideband High-Performance Sigma-Delta Modulators for High-Speed Communications [article]

Yi Yin, Technische Universität Berlin, Technische Universität Berlin, Heinrich Klar
2006
However, early signal digitization increases requirements on the analog-to-digital converters (ADCs) regarding resolution and bandwidth.  ...  In this thesis, a systematic approach for designing high-speed high-resolution Sigma-Delta modulators is introduced.  ...  Therefore, the errors are not shaped by the loop and linearization techniques are required to correct for the mismatch errors in the DAC elements.  ... 
doi:10.14279/depositonce-1414 fatcat:jss4lyfqwjhchk6ffykw7oo2e4
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