Filters








49 Hits in 5.6 sec

Design and implementation of non-linear image processing functions for CMOS image sensor

Purnawarman Musa, Sunny A. Sudiro, Eri P. Wibowo, Suryadi Harmanto, Michel Paindavoine, Tsutomu Shimura, Guangyu Xu, Linmi Tao, Jesse Zheng
2012 Optoelectronic Imaging and Multimedia Technology II  
For example, edge detection step followed by a local maxima extraction will facilitate the high-level processing like objects pattern recognition in a visual scene.  ...  For this purpose, we present in this article the design and test of a 64×64 pixels image sensor built in a standard CMOS Technology 0.35µm including non-linear image processing.  ...  If the digital value (D i ) = 1, then the value of residue is : V res (i) = 2 × V in (i) − D i V refp (3) If digital value (D i ) = 0, residual voltage is : V res (i) = 2 × V in (i) − D i V refn (4) Where  ... 
doi:10.1117/12.2000538 fatcat:27q6lrmogvfh7g2yfd4zg35bdi

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High- Performance Processing [chapter]

Vladimir G., Aleksandr I., Alexander A.
2013 Optoelectronics - Advanced Materials and Devices  
They can be regarded as a subset of OE-VLSI circuits because they consist only of arrays of photo-detectors with corresponding evaluation circuit for analogue to digital converting.  ...  "t present the situation for smart detector circuits is much easier.  ...  optoelectronic parallel-pipeline systems OEPS with command-flow D-page picture organization [ ], necessity in arrays of optic or optoelectronic triggers memory elements of picture type for storage of  ... 
doi:10.5772/54540 fatcat:4owfplhh3rfo7mki7isldvvf7m

2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66

2019 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI Aug. 2019 2963-2972 Optimal Complexity Architectures for Pipelined Distributed Arithmetic-Based LMS Adaptive Filter.  ...  Costanzo, L., +, TCSI March 2019 1291-1303 Pipeline arithmetic Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation.  ... 
doi:10.1109/tcsi.2020.2966967 fatcat:f663jj5g45e3peggn3gwn5jys4

2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI Jan. 2020 74-85 Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager.  ...  ., +, TCSI April 2020 1218-1231 Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager.  ...  ., +, 3297-3308 Self-Tuned Class-D Audio Amplifier With Post-Filter Digital Feedback Implemented on Digital Signal Controller.  ... 
doi:10.1109/tcsi.2021.3055003 fatcat:kbmst5td2bbvtl7vpbj3knnkri

Aspects of systems and circuits for nanoelectronics

K.F. Goser, C. Pacha, A. Kanstein, M.L. Rossmann
1997 Proceedings of the IEEE  
In particular, linear threshold networks, the associative matrix, self-organizing feature maps, and cellular arrays are investigated from the viewpoint of their potential significance for nanoelectronics  ...  A tremendous number of devices, a limitation of wiring, and very low power dissipation density are design constraints of future nanoelectronic circuits composed of quantum-effect devices.  ...  Computation of Arithmetic Functions with Linear Threshold Networks Before we focus on neural circuits, we outline the application of linear threshold gates (LTG's) for digital computation.  ... 
doi:10.1109/5.573741 fatcat:ck6njzh3fja27atr7vuqmsc6oe

Demonstration and architectural analysis of complementary metal-oxide semiconductor/multiple-quantum-well smart-pixel array cellular logic processors for single-instruction multiple-data parallel-pipeline processing

Jen-Ming Wu, Charles B. Kuznia, Bogdan Hoanca, Chih-Hao Chen, Alexander A. Sawchuk
1999 Applied Optics  
We present laboratory demonstrations of the system for digital image edge detection and digital video motion estimation.  ...  We present an optoelectronic-VLSI system that integrates complementary metal-oxide semiconductor͞ multiple-quantum-well smart pixels for high-throughput computation and signal processing.  ...  A parallel-pipeline smart-pixel array system such as SPARCL offers a method for running digital video motion estimation efficiently.  ... 
doi:10.1364/ao.38.002270 pmid:18319791 fatcat:kcurd3ryb5b75loll3k5vg3jga

Intensity feedback-based beam wandering mitigation in free-space optical communication using neural control technique

Arockia A Bazil Raj, Arputha J Vijaya Selvi, Kumar D Durai, Raghavan S Singaravelu
2014 EURASIP Journal on Wireless Communications and Networking  
A FSOC experimental setup is developed for the link range of 0.5 km in the college campus. A neural controller is designed for beam wandering mitigation.  ...  New design approach and architecture development for the implementation of the designed neural controller in the field-programmable gate array (FPGA) to mitigate the beam wandering are presented.  ...  A, B, C, D, E, F, and G are the main sub-circuits and a, b, c, d, e, f, and g are the pipeline stages.  ... 
doi:10.1186/1687-1499-2014-160 fatcat:niexh4qpazcb7hkezlkmaykzsm

Field Programmable Gate Array Applications—A Scientometric Review

Juan Ruiz-Rosero, Gustavo Ramirez-Gonzalez, Rahul Khanna
2019 Computation  
, digital signal processing, image and video processing, big data, computer algorithms and other applications.  ...  These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers' navigation systems  ...  A parallel implementation of the Smith-Waterman algorithm for massive sequences searching.  ... 
doi:10.3390/computation7040063 fatcat:wxtatzsvvnfopghdfl25hcfc2a

Performance constraints for onchip optical interconnects

J.H. Collet, F. Caignet, F. Sellaye, D. Litaize
2003 IEEE Journal of Selected Topics in Quantum Electronics  
This work aims at defining the marks that optoelectronic solutions will have to beat for replacing electric interconnects at chip level.  ...  The first possible application of onchip OIs is likely not for inter-block communication but for clock distribution as the energy constraints (imposed by the evolution of CMOS technology) are weaker and  ...  Acknowledgments We wish to thank two of our referees for their comments and their judicious suggestions that have contributed to improve the manuscript.  ... 
doi:10.1109/jstqe.2003.812508 fatcat:ytfz3grzhnbz3c7v2lsb24gjeu

2020 Index IEEE Journal of Solid-State Circuits Vol. 55

2020 IEEE Journal of Solid-State Circuits  
Pulsed TOF Solid-State 3-D Imaging; JSSC July 2020 1960-1970, see Qi, L., 2889-2901 Jang, S., see Kim, D., JSSC Jan. 2020 167-177 Jansson, J., see Jahromi, S., JSSC July 2020 1960-1970 Je, M  ...  Iwai, T., see Fan, Y., JSSC Feb. 2020 439-451 J Jafarlou, S., see Nazari, P., JSSC Feb. 2020 282-297 Jahromi, S., Jansson, J., Keranen, P., and Kostamovaara, J., A 32 × 128 SPAD-257 TDC Receiver IC for  ...  Multiband 5G Massive MIMO.  ... 
doi:10.1109/jssc.2021.3054535 fatcat:rfm7shuowvakfgzumgtqzlod5i

Peak Detection Based on FPGA Using Quasi-Newton Optimization Method for Femtosecond Laser Ranging

Yu Jiang, Qiang Liu, Hui Cao, Youjian Song
2020 IEEE Access  
FPGA is used to explore the possibilities of parallel architecture for the acceleration of peak detection, and realize the miniaturization of the system.  ...  For the DFLR system, the ranging error is reduced by 63.63% and the real-time updating of the ranging results is guaranteed.  ...  FPGAs are considered as a promising alternative because of their small size, massive parallelism (compared to digitizing instrument based on central processing units (CPUs)), high reconfigurability (compared  ... 
doi:10.1109/access.2020.2979268 fatcat:vqb7lzgc35c3fmipsgwu7uaxza

The M2DC Project: Modular Microserver DataCentre

Mariano Cecowski, Giovanni Agosta, Ariel Oleksiak, Michal Kierzynka, Micha vor dem Berge, Wolfgang Christmann, Stefan Krupop, Mario Porrmann, Jens Hagemeyer, Rene Griessl, Meysam Peykanu, Lennart Tigges (+13 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.  ...  medium voltage inverters 2012 [644] Test Embedded instrument for board system test 2012 [645] Medical / Image processing 3-D Daubechies with transpose-based method for medical image compression  ...  The flexibility of FPGAs is the main reason stated for choosing them to implement even uncommon switching behavior, like single to broadcast transmissions. 5) Cryptography: Massive parallelism and the  ... 
doi:10.1109/dsd.2016.76 dblp:conf/dsd/CecowskiAOKBCKP16 fatcat:bu4nbkqaejebjafrotibui6mkq

2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65

2018 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Pepe, D., +, TCSI May 2018 1495-1504 Inductance Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs.  ...  ., +, TCSI Oct. 2018 3578-3591 Digital arithmetic A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems.  ... 
doi:10.1109/tcsi.2019.2896877 fatcat:3lzpngw2ofdjhiculf7ehrjeam

Artificial neural networks in hardware: A survey of two decades of progress

Janardan Misra, Indranil Saha
2010 Neurocomputing  
Parallel digital implementations employing bit-slice, systolic, and SIMD architectures, implementations for associative neural memories, and RAM based implementations are also outlined.  ...  Hardware neural network Neurochip Parallel neural architecture Digital neural design Analog neural design Hybrid neural design Neuromorphic system FPGA based ANN implementation CNN implementation RAM based  ...  [174] suggest a bit-serial/parallel neural network implementation method for pre-trained networks using bit-serial distributed arithmetic for implementing digital filters.  ... 
doi:10.1016/j.neucom.2010.03.021 fatcat:regzu6sshvekzd5wxcuaiytgqu

Integrated photonic FFT for photonic tensor operations towards efficient and high-speed neural networks

Moustafa Ahmed, Yas Al-Hadeethi, Ahmed Bakry, Hamed Dalir, Volker J. Sorger
2020 Nanophotonics  
are fueling next generation densely interconnected intelligent photonic circuits with relevance for edge-computing 5G networks by processing tensor operations optically.  ...  Lastly, we show that, conceptually, the optical FFT and convolution-processing performance is indeed directly linked to optoelectronic device-level, and improvements in plasmonics, metamaterials or nanophotonics  ...  Harnessing the strengths of optics for emerging processors bears much potential to free circuits from charging wires, while utilizing massive parallelism paradigms [8] . : Photonic Tensor Processing paradigm  ... 
doi:10.1515/nanoph-2020-0055 fatcat:2qqgbmvnd5de3lohohmyfwyz54
« Previous Showing results 1 — 15 out of 49 results