A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
Filters
A Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability
2020
Journal of Integrated Circuits and Systems
Preserved Fulltext
Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell ...
WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. ...
Process variation immune differential 8T SRAM cell with lower power dissipation and low power during hold mode has been proposed [15] . ...
doi:10.29292/jics.v15i2.140
fatcat:33ncdqhp2vd4rfsx4bqcdom5xq
Design of Polymer-Based Trigate Nanoscale FinFET for the Implementation of Two-Stage Operational Amplifier
2022
International Journal of Polymer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
To facilitate the creation of FinFET-based circuits, including product development, a novel transistor needs a creative device basis. ...
For different circuit configurations, it also examines the DC and AC characteristics of the FinFET structure. A differential amplifier is built for RF application based on the device specifications. ...
To ease the creation of FinFET-based circuits, a novel transistor needs a creative device basis. ...
doi:10.1155/2022/3963188
fatcat:6eawmkfp6vf7jmqbffrw375bza
SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET
2014
Microelectronics and reliability
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
In this paper, we present a novel design style that reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. ...
In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously ...
This research work has been undertaken with the support of the Spanish MINECO (JCI-2010-07083 and TEC2008-01856 with FEDER funds). ...
doi:10.1016/j.microrel.2013.12.018
fatcat:vque7zamjvacbikketthw46piu
A Process Variation Tolerant Self-Compensating Sense Amplifier Design
2009
2009 IEEE Computer Society Annual Symposium on VLSI
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. ...
FinFET based Latch Sense Amplifier
Working of FinFET based Latch Type Sense Amplifier The LSA operates in two phases: pre-charge phase and the evaluation phase. ...
doi:10.1109/isvlsi.2009.50
dblp:conf/isvlsi/ChoudharyK09
fatcat:7d4ncb2rpbdxnmjhziormvjine
Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices
2005
IEEE Transactions on Electron Devices
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2008; you can also visit the original URL.
The file type is application/pdf.
power for different 3-T as well as IG FinFET logic cells; 3) IG FinFET-design-library-based circuit synthesis framework to achieve efficient low-power circuit design in IG technology. ...
In this paper, we developed semianalytical delay and power models for IG FinFET-based logic cells, and a generic efficient design library-based circuit synthesis framework. ...
His research interests include low-power, robust, and high-performance circuit design for nanoscale technologies. He has many publications in journals and conferences and several patents pending. ...
doi:10.1109/ted.2004.842713
fatcat:ki5vlrqvczegnnbc6kuszrxzky
Independently-controlled-Gate FinFET Schmitt Trigger sub-threshold SRAMs
2010
2010 IEEE International SOI Conference (SOI)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. ...
Index Terms-FinFET, low power SRAM, Schmitt Trigger, static noise margin, sub-threshold SRAM. ...
With the capability of independent gate control in double-gate FinFET devices, we propose three novel FinFET independently-controlled-gate Schmitt Trigger (IG_ST) SRAM cells (shown as IG_ST1, IG_ST2, and ...
doi:10.1109/soi.2010.5641375
fatcat:6tglotyfbzahxfulkkecnt44ou
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
2012
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. ...
Index Terms-FinFET, low power SRAM, Schmitt Trigger, static noise margin, sub-threshold SRAM. ...
With the capability of independent gate control in double-gate FinFET devices, we propose three novel FinFET independently-controlled-gate Schmitt Trigger (IG_ST) SRAM cells (shown as IG_ST1, IG_ST2, and ...
doi:10.1109/tvlsi.2011.2156435
fatcat:gmghtlep3jezhceptf7ygfyuom
Table of contents
2021
IEEE Transactions on Electron Devices
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
Schurr 3672 Ternary Logic Circuit Based on Negative Capacitance Field-Effect Transistors and Its Variation Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Palmer 3453 Design of a Fan-Out Panel-Level SiC MOSFET Power Module Using Ant Colony Optimization-Back Propagation Neural Network . . . . . . . . . . . . . . . . . . . . . . . . Y. Qian, F. Hou, J. ...
doi:10.1109/ted.2021.3087051
fatcat:udjtxiufzreflkkbxr7fdibia4
2020 Index IEEE Transactions on Nanotechnology Vol. 19
2020
IEEE transactions on nanotechnology
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
., +, TNANO 2020 500-507 Power HEMT Analysis and Optimization of GaN Based Multi-Channels FinFETs. ...
., +, TNANO 2020 439-445 Power MOSFET Analysis and Optimization of GaN Based Multi-Channels FinFETs. ...
doi:10.1109/tnano.2021.3055152
fatcat:5ilss2fujfhl7m7o5rvnjgewhm
Table of Contents
2019
2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
and Delay Optimization of FinFET based Adiabatic Logic
SRAM Cell
617-621
119
490
Performance Optimization of Dual supply voltage level shifter
using FINFET and CNTFET at 32nm technology
622 ...
Solar PV System for Rural
School Application
449-453
88
184
Design and Analysis of Gate Underlapped/Overlapped Surround
Gate Nanowire TFET for Analog Performance
454-458
89
260
Design ...
doi:10.1109/rteict46194.2019.9016925
fatcat:3azpzwfoljdhpkx5h3addkc4ga
Double-gate SOI devices for low-power and high-performance applications
2006
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
We show a variety of circuits in logic and memory that can benefit from independent gate operation of DG devices. ...
Among the various types of DG devices, quasi-planar SOI FinFETs are easier to manufacture compared to planar double-gate devices. ...
Based on the idea of IG skewing, a new skewed CMOS logic style is presented to improve performance and to reduce power dissipation. ...
doi:10.1109/vlsid.2006.74
dblp:conf/vlsid/RoyMMABC06
fatcat:3eoijixwczdpdpqu54ksk3as6u
2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26
2018
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
., see 2723-2736
, VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957 ...
., +, TVLSI Feb. 2018 319-328 Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. ...
., +, TVLSI April 2018 744-755 Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. ...
doi:10.1109/tvlsi.2019.2892312
fatcat:rxiz5duc6jhdzjo4ybcxdajtbq
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS
2008
Proceedings of the IEEE
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation. 1 Channel length L, which is ...
How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. ...
Program, in particular, their support of C2S2. They are also grateful to their many faculty and student colleagues in C2S2 for their ideas and inputs on this paper. ...
doi:10.1109/jproc.2007.911072
fatcat:dxmkxqiazffjzfv24okubw4zeu
Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things
2017
Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
The uses of emerging technologies and lightweight encryption for correlation power analysis against side channel attack, silicon nanowire polymorphic gates, and all-spin logic devices for deception and ...
Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon ...
Jin Lin contributes to low power SAR ADC and hybrid ΔƩ SAR ADC designs. Qutaiba Alasa makes a contribution in polymorphic gate logic locking using silicon nanowire and all spin logic devices. ...
doi:10.3390/electronics6030067
fatcat:ozssarlb2ng5pcdsupo2hljyna
Plenary Session
2021
2021 IEEE International Electron Devices Meeting (IEDM)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
The first paper offers new application opportunities of eMRAM combined with CMOS Image sensor at 28nm logic platform. ...
The second paper presents a design scheme to improve write energy and write speed of STT-MRAM cells, essential for MCU applications. ...
The fourth paper is an invited paper giving an overview of the latest advancements in the design and performance of ultra-high power silicon devices. ...
doi:10.1109/iedm19574.2021.9720570
fatcat:xvmkuujuyraujbtixrhdycd5sq
« Previous
Showing results 1 — 15 out of 98 results