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A 3D FPGA Architecture to Realize Simple Die Stacking

Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2015 IPSJ Transactions on System LSI Design Methodology  
This architecture can be expanded to more than two layers by stacking multiples of the same die.  ...  The functionally distributed architecture consists of two wafers, a logic layer and a routing layer, and is stacked by a face-down process technology.  ...  Conclusion In this paper we proposed a functionally distributed type and a spatially distributed type of 3D FPGA architecture to allow simple die stacking.  ... 
doi:10.2197/ipsjtsldm.8.116 fatcat:c3byrcdxqvc2jpao4c2v25uj4e

TLB and Pagewalk Performance in Multicore Architectures with Large Die-Stacked DRAM Cache [article]

Adarsh Patil
2020 arXiv   pre-print
The recently evolved die-stacked DRAM technology promises a high bandwidth and large last-level cache, in the order of Gigabytes, closer to the processors.  ...  Hence, we are interested in exploring novel address translation mechanisms, commensurate to the size and latency of stacked DRAM.  ...  The advent of die-stacking technology [7] provides a way to integrate disparate silicon die with better interconnects.  ... 
arXiv:2002.01073v1 fatcat:zd6hpcveh5dxpaazki3vusjhzm

Die-stacked DRAM caches for servers

Djordje Jevdjic, Stavros Volos, Babak Falsafi
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
This paper introduces Footprint Cache, an efficient die-stacked DRAM cache design for server processors.  ...  Recent research advocates using large die-stacked DRAM caches to break the memory bandwidth wall. Existing DRAM cache designs fall into one of two categories -block-based and pagebased.  ...  In this paper we make the following contributions: • We propose Footprint Cache, a novel die-stacked DRAM cache architecture that combines the benefits of block-and pagebased designs through footprints  ... 
doi:10.1145/2485922.2485957 dblp:conf/isca/JevdjicVF13 fatcat:bl2twnnncjhpvmby7khhoj3lwy

Resilient die-stacked DRAM caches

Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
2013 Proceedings of the 40th Annual International Symposium on Computer Architecture - ISCA '13  
Die-stacked DRAM can provide large amounts of in-package, highbandwidth cache storage.  ...  While conventional off-chip memory provides ECC support by adding one or more extra chips, this may not be practical in a 3D stack.  ...  Die-stacked DRAM Die-stacked DRAM consists of one or more layers of DRAM with a very-wide data interface connecting the DRAM stack to whatever it is stacked with (e.g., a processor die).  ... 
doi:10.1145/2485922.2485958 dblp:conf/isca/SimLSO13 fatcat:n6uix5stxnag7dambcoqhtoy4a

A Software-Managed Approach to Die-Stacked DRAM

Mark Oskin, Gabriel H. Loh
2015 2015 International Conference on Parallel Architecture and Compilation (PACT)  
How to integrate this technology into the overall architecture of a computing system is an open question.  ...  Advances in die-stacking (3D) technology have enabled the tight integration of significant quantities of DRAM with high-performance computation logic.  ...  We begin, however, in the next section with background on die-stacked DRAM and a review of past architectural approaches in this design space. II. BACKGROUND A.  ... 
doi:10.1109/pact.2015.30 dblp:conf/IEEEpact/OskinL15 fatcat:fn4mpetyhfhp5fven24s3iort4

Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures

Wangyuan Zhang, Tao Li
2009 2009 18th International Conference on Parallel Architectures and Compilation Techniques  
Consequently, the refresh frequency of 3D die-stacked DRAM needs to be doubled (or more) to retain data at the expense of additional power overhead.  ...  In this work, we investigate using Phase-change Random Access Memory (PRAM) as a promising candidate to achieve scalable, low power and thermal friendly memory system architecture in the upcoming 3D-stacking  ...  On the other hand, the high temperature driven operations and low stand-by power make PRAM more thermal friendly to 3D die stacked memory architecture.  ... 
doi:10.1109/pact.2009.30 dblp:conf/IEEEpact/ZhangL09 fatcat:fvo6bzaxljckdbsvrt3oiofzhq

Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories

Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
Die-stacked DRAM is a technology that will soon be integrated in high-performance systems.  ...  Recent studies have focused on hardware caching techniques to make use of the stacked memory, but these approaches require complex changes to the processor and also cannot leverage the stacked memory to  ...  With die-stacked DRAM, the bandwidths are significantly higher.  ... 
doi:10.1109/hpca.2015.7056027 dblp:conf/hpca/MeswaniBRSIL15 fatcat:askhggskjvhctoyvll2kquxtmm

i-MIRROR: A Software Managed Die-Stacked DRAM-Based Memory Subsystem

Jee Ho Ryoo, Karthik Ganesan, Yao-Min Chen, Lizy Kurian John
2015 2015 27th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)  
Our scheme maintains the pages in the off-chip and the die-stacked DRAM in a synchronized/mirrored state by exploiting the parallel loading capability to the die-stacked and off-chip DRAM from the disk  ...  This eliminates the need for physical page movement to the slower off-chip DRAM upon eviction from the die-stacked DRAM.  ...  Die-stacked DRAM (DSD) rises as an emerging solution to address the problems in today's off-chip memory bandwidth.  ... 
doi:10.1109/sbac-pad.2015.34 dblp:conf/sbac-pad/RyooGCJ15 fatcat:i7gs7g2fqzgmrpnvvpkvhmeqbq

Thermal Management of Die Stacking Architecture That Includes Memory and Logic Processor

B.P. Dewan-Sandur, A. Kaisare, D. Agonafer, D. Agonafer, C. Amon, S. Pekin, T. Dishongh
56th Electronic Components and Technology Conference 2006  
Previously, present authors reported on the thermal challenges of various die stacking architectures that included memory (volatile and non-volatile) only.  ...  Package architectures evaluated were rotated stack, staggered stack utilizing redistributed pads, and stacking with spacers, while all other parameters were held constant.  ...  Stack Architecture vs Percentage Temperature Reduction Table 1 : 1 Package Dimensions Component Dimension (mm) Memory -Die Stack 4 x 6 x 0.1 Memory -Bottom Die 9 x 13 x 0.1 Logic Die 12 x 12 x  ... 
doi:10.1109/ectc.2006.1645929 fatcat:rcwvwqnfana53oltzk6rrxoi4a

Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology

K. Puttaswamy, G.H. Loh
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)  
In particular, a 3D implementation of 256-entry physical register file in a two-die stack achieves a 24.1% latency improvement with a simultaneous energy reduction of 58.5%, while a four-die version achieves  ...  3D integration is a new technology that will greatly increase transistor density while providing faster on-chip communication. 3D integration stacks multiple die connected with a very high-density and  ...  The advantage of a F2B organization is that an arbitrary number of die can be stacked; Figure 1 (b) shows a four-die F2B stack.  ... 
doi:10.1109/isvlsi.2006.56 dblp:conf/isvlsi/PuttaswamyL06 fatcat:l52t73duszcufg2bey2ntvhsjq

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers

Christos Papameletis, Brion Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen
2015 IEEE design & test  
next die in the stack.  ...  The secondary port of one die fits to the primary port of the next die in the stack.  ... 
doi:10.1109/mdat.2015.2424422 fatcat:36q7xllvbzdupcbgv2gjqegpty

Test-architecture optimization for TSV-based 3D stacked ICs

Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree
2010 2010 15th IEEE European Test Symposium  
We consider 3D-SICs with both fixed given and yet-to-be-designed test architectures on each die and show that both corresponding problem variants are N P-hard.  ...  In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using Through-Silicon Vias (TSVs) technology.  ...  ILP models for test architecture design for each die in a stack is presented in [16] .  ... 
doi:10.1109/etsym.2010.5512787 dblp:conf/ets/NoiaGCMV10 fatcat:xe7izohd4zhhdedn4dx5hoycky

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Christos Papameletis, Brion Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui
2013 2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)  
Previously, we defined, implemented, and automated a 3D-DfT (Design-for-Test) architecture that provides modular test access for 3D-SICs containing monolithic logic dies in a single-tower stack.  ...  In this paper, our existing 3D-DfT architecture is extended with support for wrapped embedded IP cores and multi-tower stacks and its implementation is automated with industrial electronic design automation  ...  located in the bottom die of the stack.  ... 
doi:10.1109/ets.2013.6569350 dblp:conf/ets/PapameletisKCMH13 fatcat:ln36ida2tvanfiz7h6xlnuxxhi

Time-multiplexed test access architecture for stacked integrated circuits

Muhammad Adil Ansari, Jihun Jung, Dooyoung Kim, Sungju Park
2016 IEICE Electronics Express  
Due to ever-increasing gap between (1) the tester-channel and scan-shift frequencies, and (2) the wafer-level and package-level test frequencies, the tester-channel frequency is underutilized for stacked-ICs  ...  Thus, we present a novel time-multiplexed test access architecture for SICs that complies with P1838 and it significant reduces test time, which reduction is observed on a synthetic SIC based on ITC'02  ...  The proposed architecture connects all of the test data/control lines to each die wrapper in parallel, unlike the conventional P1838 architecture.  ... 
doi:10.1587/elex.13.20160314 fatcat:qpemtjbnungodb7noz5vsgd6xq

Optimization methods for post-bond die-internal/external testing in 3D stacked ICs

Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen
2010 2010 IEEE International Test Conference  
Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there is a need to test multiple subsequent partial stacks during 3D assembly.  ...  We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test.  ...  ILP models for test architecture design for each die in a stack are presented in [16] .  ... 
doi:10.1109/test.2010.5699219 dblp:conf/itc/NoiaCM10 fatcat:ahygcfsalvac3pmszkwcyracmq
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