Filters








7,555 Hits in 7.1 sec

Diagnosis of full open defects in interconnect lines with fan-out

R. Rodriguez-Montanes, D. Arumi, J. Figueras, S. Einchenberger, C. Hora, B. Kruseman
2010 2010 15th IEEE European Test Symposium  
Widely used interconnect full open diagnosis procedures are based on the assumption that neighbouring lines determine the voltage of the defective line.  ...  As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes a key factor.  ...  DIAGNOSIS OF INTERCONNEC FULL OPEN DEFECTS For an accurately diagnosis of interconnect opens, we consider any possible open location along the defective line using the full open segment (FOS) model [17  ... 
doi:10.1109/etsym.2010.5512752 dblp:conf/ets/Rodriguez-MontanesAFEHK10 fatcat:jobed2tc2nhp7gf7mghf42qjg4

Gate Leakage Impact on Full Open Defects in Interconnect Lines

Daniel Arumi, Rosa Rodriguez-Montanes, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line.  ...  This new phenomenon influences the behavior of circuits with interconnect full open defects.  ...  Subsequently, an in-house diagnosis tool was used and it was concluded that this device might contain an interconnect full open defect.  ... 
doi:10.1109/tvlsi.2010.2077315 fatcat:rv4oepo3ujhi3odrq3yrydbm7m

Incremental fault diagnosis

J.B. Liu, A. Veneris
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Circuit simulation, fault diagnosis, open-interconnect, very large scale integration (VLSI).  ...  Diagnosis of today's complex defects is a challenging problem due to the explosion of the underlying solution space with the increasing number of fault locations and fault models.  ...  Amiri in earlier versions of this work. They also thankfully acknowledge the associate editor and the anonymous reviewers of this paper for comments that improved its presentation.  ... 
doi:10.1109/tcad.2004.841070 fatcat:b3aqpl73bzgppf2gocqff2sjuy

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Zhan Gao, Min-Chun Hu, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Erik Jan Marinissen
2021 Journal of electronic testing  
The full set is stored for the diagnosis and failure analysis.  ...  However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage 1 unaffordable.  ...  The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material.  ... 
doi:10.1007/s10836-021-05943-3 fatcat:ksw7d4lvqnfbbeoilpk4rtxbqy

Test Strategies for Multivoltage Designs [chapter]

Saqib Khursheed, Bashir M. Al-Hashimi
2009 Power-Aware Testing and Test Strategies for Low Power Devices  
This chapter presents a coherent overview of recently reported research in testing strategies for multi-voltage designs including defect modelling, test generation and DFT solutions.  ...  Some manufacturing defects have Vdd-dependency, which implies defects can become active only at certain power supply setting, leading to reduced defect coverage.  ...  Ilia Polian (Albert-Ludwigs-University of Freiburg) for useful comments and EPSRC (U.K) for supporting this work under Grant EP/DO57663/1.  ... 
doi:10.1007/978-1-4419-0928-2_8 fatcat:sjivk55a2fboznqwcwoahghjiq

Modeling manufacturing process variation for design and test

S Kundu, A Sreedhar
2011 2011 Design, Automation & Test in Europe  
This presentation reviews currently available defect modeling and test solutions and summarizes open issues faced by the industry today.  ...  With these new solutions come an increasing number of defect mechanisms.  ...  On the other hand, some of the examples of inter-cell defects are opens and bridges, line and via disappearances, stress voiding etc. These cases have to modeled and treated separately.  ... 
doi:10.1109/date.2011.5763192 dblp:conf/date/KunduS11 fatcat:7b6hpuheqvhnppznosav2kvkia

Net diagnosis using stuck-at and transition fault models

Lixing Zhao, Vishwani D. Agrawal
2012 2012 IEEE 30th VLSI Test Symposium (VTS)  
Diagnosis is the procedure used when circuit verification fails. Determining the cause of the failure and finding the possible defect locations are included in diagnosis.  ...  In this thesis, a procedure of diagnosing multiple net-faults is proposed. Many previous studies on fault diagnosis mainly focused on single failures. However, Vishwani D. Agrawal, the James J.  ...  Open Fault Diagnosis Open fault model usually is used for interconnection defect diagnosis.  ... 
doi:10.1109/vts.2012.6231106 dblp:conf/vts/ZhaoA12 fatcat:cbnggxfzlrautlkmfxlx5q3dyi

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey

A. Doumar, H. Ito
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
These topics include FPGA fault detection, FPGA fault diagnosis, FPGA defect tolerance, and FPGA fault tolerance. This paper provides a guided tour to the approaches related to these topics.  ...  Index Terms-Defect tolerance, fault detection, fault diagnosis, fault model, fault tolerance, reconfiguration, SRAM-based field programmable gate arrays (FPGAs), test, yield improvement.  ...  One consists of diagnosing faults using the BIST method for interconnect fault diagnosis and the other is the non-BIST method for interconnect diagnosis.  ... 
doi:10.1109/tvlsi.2002.801609 fatcat:3nprfsfb2rcd5f4wtmqq66fhaq

Multilevel full-chip routing with testability and yield enhancement

Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu-E Chen
2005 Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05  
We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening  ...  Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme for interconnects based on the popular IEEE Standard 1500 are integrated into the multilevel routing framework  ...  This approach is specifically important as the probability of back-end-of-line defects (i.e., high-resistance via and interconnect defects) increases [4] .  ... 
doi:10.1145/1053355.1053362 dblp:conf/slip/LiLCSC05 fatcat:rtkimxs7ingppmv7xq6hqakjlu

Multilevel Full-Chip Routing With Testability and Yield Enhancement

Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening  ...  Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme for interconnects based on the popular IEEE Standard 1500 are integrated into the multilevel routing framework  ...  This approach is specifically important as the probability of back-end-of-line defects (i.e., high-resistance via and interconnect defects) increases [4] .  ... 
doi:10.1109/tcad.2007.895587 fatcat:t4des4udfjgxfnvb7kcumnktei

BIST Based Interconnect Fault Location for FPGAs [chapter]

Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko
2004 Lecture Notes in Computer Science  
A Built-In Self-Test (BIST) method that can efficiently identify the exact location of the interconnect fault is introduced.  ...  This procedure forms the first step of a new interconnect defect tolerant scheme that offers the possibility of using larger and more cost effective devices that contain interconnect defects without compromising  ...  Failed devices are mainly discarded even though the total amount of resources affected by a physical defect is minimal. Some of these devices can be used, albeit not in full capacity.  ... 
doi:10.1007/978-3-540-30117-2_34 fatcat:eysjqfqnkrcqplgbt73jn3osdy

Diagnosing Multiple Byzantine Open-Segment Defects Using Integer Linear Programming

Chen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen
2011 Journal of electronic testing  
Faulty behaviors of open-segment defects are non-deterministic due to the Byzantine effect induced by the physical circuit layout.  ...  Therefore, we propose a threestage diagnosis approach for finding multiple opensegment defects.  ...  Enhancing the diagnosis of full open defects in interconnect is proposed in [18] where vias and metal lines are considered.  ... 
doi:10.1007/s10836-011-5265-0 fatcat:456kvl2xdbbvfmnae2rnwzzugy

Fault diagnosis of TSV-based interconnects in 3-D stacked designs

J. Rajski, J. Tyszer
2013 2013 IEEE International Test Conference (ITC)  
This paper describes a procedure for deriving fault diagnosis test sequences to identify single and multiple defective TSVs.  ...  Additional experimental results obtained for pseudorandom patterns illustrate feasibility and robustness of the proposed test schemes in terms of their detection and diagnostic capabilities and are reported  ...  of TSV opens as a key part of fault diagnosis.  ... 
doi:10.1109/test.2013.6651894 dblp:conf/itc/RajskiT13 fatcat:xnvanbdakng4fa3b6qjddl3zyu

Fault Testing and Diagnosis of Sram based FBGA using Built-In-Self-Test-Architecture

Nagma. P, Ramachandran. S, Sathishkumar. E
2018 International Journal of Trend in Scientific Research and Development  
The target fault detection/diagnosis of the proposed BIST structure are open/short and delay faults in the wire channels, stuck on/off faults in PSs, andstuck-at-0/1 faults in LUTs.  ...  Built in Self-Test (BIST) is a design technique that allows a circuit to test itself .The proposed method of a built-in self-test (BIST) design for fault detection and fault diagnosis of static-RAM (SRAM  ...  For interconnect diagnosis, multiple faults (open, stuck-at, or bridging fault) can be uniquely identified.  ... 
doi:10.31142/ijtsrd9415 fatcat:wtdhleviqjaj5if7pgdynwcire

Using embedded FPGAs for SoC yield improvement

M. Abramovici, C. Stroud, M. Emmert
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
In this paper we show that an embedded FPGA core is an ideal host to implement infrastructure IP for yield improvement in a bus-based SoC.  ...  We show how an FPGA core can provide embedded testers for other cores in the SoC, so that cores designed to be tested with external vectors can be tested with BIST, and the entire SoC can be tested with  ...  InFigure 7, the WUTs are shown by bold lines, and the activated (closed) CIPs are shown in gray, while the open CIPs are white.  ... 
doi:10.1109/dac.2002.1012717 fatcat:ov3bwhjztfghdc2i3ezbbhpuva
« Previous Showing results 1 — 15 out of 7,555 results