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Thread-Sensitive Instruction Issue for SMT Processors

B. Robatmili, N. Yazdani, S. Sardashti, M. Nourani
2004 IEEE computer architecture letters  
In this paper, we propose a thread sensitive issue policy for a partitioned SMT processor which is based on a thread metric.  ...  We propose the number of ready-to-issue instructions of each thread as priority metric. To evaluate our method, we have developed a reconfigurable SMT-simulator on top of the SimpleScalar Toolset.  ...  Tullsen et al. proposed their SMT architecture as an extension to Superscalar processors and studied fetch policies for their SMT processor [6] .  ... 
doi:10.1109/l-ca.2004.9 fatcat:r3g3x3yjirgwlc56zfvaft5kea

Probabilistic job symbiosis modeling for SMT processor scheduling

Stijn Eyerman, Lieven Eeckhout
2010 SIGARCH Computer Architecture News  
(sample, optimize, symbios) approach for a two-thread SMT processor, and an average 19% (and up to 45%) reduction in job turnaround time for a four-thread SMT processor.  ...  The model, which uses per-thread cycle stacks computed through a previously proposed cycle accounting architecture, is simple enough to be used in system software.  ...  Acknowledgements We thank the reviewers for their constructive and insightful feedback. Stijn Eyerman is supported through a postdoctoral fellowship by the Research Foundation-Flanders (FWO).  ... 
doi:10.1145/1735970.1736033 fatcat:rj7neqxaljfpvluca2comsdsdm

Simultaneous thin-thread processors for low-power embedded systems

Won W. Ro, Jaeyoung Yi, Joon-Sang Park, Joonseok Park
2008 IEICE Electronics Express  
A drawback is that the conventional design of the superscalar processors possesses inherent complexity and power problems which are not easily acceptable in the domain of embedded processors.  ...  In this paper, we investigate the possibility to use multi-threaded processors to solve the problems with the traditional superscalar processors in embedded systems.  ...  Simultaneous thin-threading: SMT for embedded processors Simultaneous multithreading was originally developed to solve the long latency and pipeline stalling problem of the superscalar architecture.  ... 
doi:10.1587/elex.5.802 fatcat:axoa4v4bfje63hogzswwg3shci

Probabilistic job symbiosis modeling for SMT processor scheduling

Stijn Eyerman, Lieven Eeckhout
2010 Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems - ASPLOS '10  
(sample, optimize, symbios) approach for a two-thread SMT processor, and an average 19% (and up to 45%) reduction in job turnaround time for a four-thread SMT processor.  ...  The model, which uses per-thread cycle stacks computed through a previously proposed cycle accounting architecture, is simple enough to be used in system software.  ...  Acknowledgements We thank the reviewers for their constructive and insightful feedback. Stijn Eyerman is supported through a postdoctoral fellowship by the Research Foundation-Flanders (FWO).  ... 
doi:10.1145/1736020.1736033 dblp:conf/asplos/EyermanE10 fatcat:bvepqdfh4jacpooq2hdwytvbhu

Probabilistic job symbiosis modeling for SMT processor scheduling

Stijn Eyerman, Lieven Eeckhout
2010 SIGPLAN notices  
(sample, optimize, symbios) approach for a two-thread SMT processor, and an average 19% (and up to 45%) reduction in job turnaround time for a four-thread SMT processor.  ...  The model, which uses per-thread cycle stacks computed through a previously proposed cycle accounting architecture, is simple enough to be used in system software.  ...  Acknowledgements We thank the reviewers for their constructive and insightful feedback. Stijn Eyerman is supported through a postdoctoral fellowship by the Research Foundation-Flanders (FWO).  ... 
doi:10.1145/1735971.1736033 fatcat:b3pjrldqurhdrbmimfgp2xjsie

Architectural Support for Network Applications on Simultaneous MultiThreading Processors

Kyueun Yi, Jean-Luc Gaudiot
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
The goal of this paper is to evaluate the applicability and efficiency of Simultaneous Multi-Threaded (SMT) as a network processor.  ...  Hence, new architectures should be designed for the programmable network processors of the future.  ...  We have proposed and evaluated a packet dependency solution for SMT processors. The proposed strategy consists of packet schedulers and of a Load/Store instruction scheduler.  ... 
doi:10.1109/ipdps.2007.370236 dblp:conf/ipps/YiG07 fatcat:4vropjc5w5bt3gcczn7c5dbqkm

Exploring chip-multiprocessors in deeply-embedded real-time computing

Xuan Qi
2008 ACM SIGBED Review  
In this essay, I propose the application of CMP in deeplyembedded real-time system.  ...  As an energy efficient high-performance architecture, chip multiprocessor (CMP) can be deployed in deeply-embedded real-time computing.  ...  However, for the tightly-coupled CMP/SMT processors where processing cores may share L2 cache and even functional units, the problem of nonpredictable performance for applications executing on CMP/SMT-based  ... 
doi:10.1145/1366283.1366296 fatcat:p6f3gmhxrvfsncsd43ov6vk7ti

An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors [chapter]

Matthew Curtis-Maury, Xiaoning Ding, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos
2008 Lecture Notes in Computer Science  
We find that the high level of resource sharing in SMTs results in performance complications, should more than 1 thread be assigned on a single physical processor.  ...  Multiprocessors based on simultaneous multithreaded (SMT) or multicore (CMP) processors are continuing to gain a significant share in both highperformance and mainstream computing markets.  ...  Acknowledgements This work is supported by an NSF ITR grant (ACI-0312980), an NSF CAREER award (CCF-0346867) and the College of William and Mary.  ... 
doi:10.1007/978-3-540-68555-5_11 fatcat:5sdth4krs5b3hhnsht24ymz5k4

Next Generation Embedded Processor Architecture for Personal Information Devices [chapter]

In-Pyo Hong, Yong-Joo Lee, Yong-Surk Lee
2006 Lecture Notes in Computer Science  
In this paper, we developed a low-cost SMT architecture model and compared its performance to other architectures including scalar, superscalar and multiprocessor.  ...  In this paper, we proposed a processor architecture that is suitable for next generation embedded applications, especially for personal information devices such as smart phones, PDAs, and handheld computers  ...  In-order SMT Architecture We developed an SMT architecture that executes instructions in program order.  ... 
doi:10.1007/11802167_47 fatcat:t73s55vutnbjhmunmeqvtlb6wy

Evaluating OpenMP on Chip MultiThreading Platforms [chapter]

Chunhua Liao, Zhenying Liu, Lei Huang, Barbara Chapman
2008 Lecture Notes in Computer Science  
It may be implemented through several physical processor cores in one chip (a Chip Multiprocessor, CMP) [17], a single core processor with replication of features to maintain the state of multiple threads  ...  simultaneously (Simultaneous multithreading, SMT) [26] or the combination of CMP and SMT [10] .  ...  ACKNOWLEDGEMENTS We thank Sun Microsystems Inc. for loaning the Sun Fire V490 machine to the Computer Science Department at University of Houston (UH).  ... 
doi:10.1007/978-3-540-68555-5_15 fatcat:g6r6utog7ndchd6tjm2m4vinka

Simultaneous multithreading: a platform for next-generation processors

S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, R.L. Stamm, D.M. Tullsen
1997 IEEE Micro  
We also thank Jennifer Anderson of DEC Western Research Laboratory for copies of the SpecFP95 benchmarks, parallelized by the most recent version of the SUIF compiler, and Sujay Parekh for comments on  ...  Acknowledgments We thank John O'Donnell of Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corp. for the source to the Alpha AXP version of the Multiflow compiler.  ...  SMT model We derived our SMT model from a high-performance, outof-order, superscalar architecture whose dynamic scheduling core is similar to that of the Mips R10000.  ... 
doi:10.1109/40.621209 fatcat:zmx4yx2flnfazi3b6zdwhavnam

The energy efficiency of CMP vs. SMT for multimedia workloads

Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, Eric Debes
2004 Proceedings of the 18th annual international conference on Supercomputing - ICS '04  
We perform this comparison for a large number of performance points derived using different processor architectures and frequencies/voltages.  ...  This paper compares the energy efficiency of chip multiprocessing (CMP) and simultaneous multithreading (SMT) on modern out-of-order processors for the increasingly important multimedia applications.  ...  To get the best of both worlds, for four-thread workloads, we study a hybrid CMP/SMT architecture (HYB) where a CMP is built out of SMT cores (e.g., IBM Power5).  ... 
doi:10.1145/1006209.1006238 dblp:conf/ics/SasankaACD04 fatcat:mojecm2mdjemlot6xxjr52pfme

Probabilistic modeling for job symbiosis scheduling on SMT processors

Stijn Eyerman, Lieven Eeckhout
2012 ACM Transactions on Architecture and Code Optimization (TACO)  
(sample, optimize, symbios) approach for a two-thread SMT processor, and an average 19% (and up to 45%) reduction in job turnaround time for a four-thread SMT processor.  ...  Symbiotic job scheduling improves simultaneous multithreading (SMT) processor performance by coscheduling jobs that have "compatible" demands on the processor's shared resources.  ...  ACKNOWLEDGMENTS We thank the reviewers for their constructive and insightful feedback.  ... 
doi:10.1145/2207222.2207223 fatcat:w366yp36sza3tdb2qn6olcs4fq

Extended Split-Issue

Bharath Iyer, Sadagopan Srinivasan, Bruce Jacob
2004 SIGARCH Computer Architecture News  
The technique can be used in both single-threaded and multi-threaded architectures to achieve a level of flexibility heretofore unavailable in the VLIW arena.  ...  XSI provides a designer the freedom of disassociating the hardware implementation of the NUAL VLIW processor from the instruction set architecture.  ...  ACKNOWLEDGEMENTS The authors would like to thank Brinda Ganesh, Arunchandar Vasan and the anonymous reviewers for their valuable feedback.  ... 
doi:10.1145/1028176.1006731 fatcat:syrdamphgvhfbekjiz2cjltcli

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
A multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline.  ...  Unused instruction slots, which arise from latencies during the pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded  ...  ACKNOWLEDGMENTS The authors would like to thank anonymous reviewers for many valuable comments.  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi
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