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Developing Synthesis Flows Without Human Knowledge [article]

Cunxi Yu and Houping Xiao and Giovanni De Micheli
2019 arXiv   pre-print
Mostly, the flows are developed based on the knowledge of the experts.  ...  However, due to the large search space of design flows and the increasing design complexity, developing Intellectual Property (IP)-specific synthesis flows providing high Quality of Result (QoR) is extremely  ...  Second, the design flows are mostly developed by the EDA developers and users based on their knowledge and user experience, with many testing iterations and intensive supervision.  ... 
arXiv:1804.05714v3 fatcat:vtcpekeoubf7lntegwcp4z5ecy

Design Technology for Systems-on-Chip [chapter]

Raul Camposano, Don MacMillen
2002 IFIP Advances in Information and Communication Technology  
Interconnect delay became dominant in many designs at O.18J.1I1l; to obtain timing closure, it was necessary to unify synthesis and placement.  ...  Moving forward, increasing degradation of signal integrity will be caused by capacitive cross coupling, by inductive effects and by several other physical effects.  ...  Finally, system design today is mostly IP-based. Processors enable the implementation of large parts of functionality in SW.  ... 
doi:10.1007/978-0-387-35597-9_8 fatcat:re5jice2l5cxtmcgyggg3aglyi

Towards an Ontology-driven Intellectual Properties reuse for Systems On Chip design

Fateh Boutekkouk
2021 International journal of computers and communications  
To address this problem, we propose to develop an IPs reuse specific ontology that facilitates IPs reuse at many levels of abstraction and independently from any design language or tool.  ...  Intellectual Properties reuse has gained widespread acceptance in System-On-Chip design to manage the complexity and shorten the time-to-market.  ...  IP reuse based-design is becoming recently a standard for time-to-market driven industry. Unfortunately, this IP based design is not free of considerable effort.  ... 
doi:10.46300/91013.2021.15.13 fatcat:uyfpnfksv5f6rd26qatva23pi4

Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications

Chulho Shin, Peter Grun, Nizar Romdhane, Christopher Lennard, Gabor Madl, Sudeep Pasricha, Nikil Dutt, Mark Noll
2007 Design automation for embedded systems  
Springer Enabling heterogeneous cycle-based and event-driven simulation  ...  design flows.  ...  The knowledge about a design being data-path or control-dominated is a well known factor in influencing the best style of synthesis optimization.  ... 
doi:10.1007/s10617-007-9003-x fatcat:ewdww5lwnvc4tinvf5an2fy3ae

Guest Editors' Introduction: DFM Drives Changes in Design Flow

J. Carballo, Y. Zorian, R. Camposano, A.J. Strojwas, J.K. Kibarian, D. Wassung, A. Alexanian, S. Wigley, N. Kelly
2005 IEEE Design & Test of Computers  
The most commonly used DFM techniques are based on judiciously including manufacturability criteria in the design flow, and can dramatically impact the business performance of chip manufacturers.  ...  These drivers are forcing designers to change traditional design flows.  ...  The Future of DFM mize most infrastructure IP blocks individually, without any special knowledge of the independently developed physical IP provided by IP vendors.  ... 
doi:10.1109/mdt.2005.61 fatcat:hgrbagcembgvjdzvwuxhc4vvvi

Panel: what is the proper system on chip design methodology?

R. Goering, S.J. Krolikoski
1999 Proceedings 1999 Design Automation Conference (Cat No 99CH36361) DAC-99/1581130929  
On the one hand, it is posited in the Reuse Methodology Manual, that a logic synthesis-based design methodology can be used effectively to develop system chips.  ...  Our contention that today the only complete pratical next generation digital SoC verification environment is based on hardware emulation that accomodates all representations of the IP, synthesizable testbenches  ...  Nothing you do in the integration flow can make up for poorly designed IP. Well-designed IP can be integrated into a wide variety of flows.  ... 
doi:10.1109/dac.1999.782242 fatcat:6572qzm26rbu5fzuuexjwrb2oi

Heterogeneous Systems on Chip and Systems in Package

I. O'Connor, B. Courtois, K. Chakrabarty, N. Delorme, M. Hampton, J. Hartung
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
A means to distinguish the various forms of heterogeneity is given, with an estimation of the maturity of design and modeling techniques with respect to various physical domains.  ...  This paper discusses several forms of heterogeneity in systems on chip and systems in package.  ...  Further, the question of knowledge management and IP re-use arises in order to ensure the preservation of know-how and reduce time-to-fab.  ... 
doi:10.1109/date.2007.364683 dblp:conf/date/OConnorCCDHH07 fatcat:5m2bmusl3rfahe77sj267xrzme

A design flow tailored for self dynamic reconfigurable architecture

Fabio Cancare, Marco D. Santambrogio, Donatella Sciuto
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
In this paper the authors introduce a new design framework which amends this lack. In particular the paper describes the entire low level design flow onto which the framework is based.  ...  The need of a comprehensive tool which can guide designers through the whole implementation process is becoming stronger.  ...  Nowadays, a novel design flow based on the module-based approach has been introduced: the Early Access Partial Reconfiguration (EAPR) [4] .  ... 
doi:10.1109/ipdps.2008.4536526 dblp:conf/ipps/CancareSS08 fatcat:keqlylytjjemldquppur2hk5a4

A reuse-based framework for the design of analog and mixed-signal ICs

Rafael Castro-Lopez, Francisco V. Fernandez, Angel Rodriguez Vazquez, Jose F. Lopez, Francisco V. Fernandez, Jose Maria Lopez-Villegas, Jose M. de la Rosa
2005 VLSI Circuits and Systems II  
The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the  ...  To extend the notion of library-based approaches, and thereby reduce overall design time, reuse and capturing AMS designers' expertise should be a major concern. 2. Improve automated synthesis.  ...  ACKNOWLEDGMENTS This work has been partially supported by project TEC2004-01752, funded by the Spanish Ministry of Education and Science.  ... 
doi:10.1117/12.607930 fatcat:qk2lkvujerg6hduekz7vp5atea

C-based SoC design flow and EDA tools: an ASIC and system vendor perspective

K. Wakabayashi, T. Okamoto
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In reality, however, more than 80% of chips cannot meet the original development schedule even now, since the schedule tends to be decided based on a time-to-market plan and not by summing up the necessary  ...  Then, we discusses the possibility of incorporating physical design feature into the C-based SoC design environment.  ...  Kawaguchi for his discussion on Design Pattern and UML modeling, and K. Oyama for contribution on behavior IPs and Fig. 7 . Finally, they would like to thank T.  ... 
doi:10.1109/43.898829 fatcat:qxt6wpnijbc7bccbfqtphac4ua

Panel: "DFM/DFY: Should You Trust the Surgeon or the Family Doctor?"

Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
This panel will examine these two approaches from high-level design all the way to manufacturing. We have assembled a set of panelists that represent a broad crosssection of semiconductor industry.  ...  As in real life, "surgery" and "medicine" represent two different schools of thought in the DFM/DFY arena. Both involve risks.  ...  For soft IP, recommendations for use of physical IP as well as DFM-friendly reference flows can be provided.  ... 
doi:10.1109/date.2007.364631 dblp:conf/date/Casale-RossiSADGMPS07 fatcat:vhxjam7rt5bermvz6q6dvg7idm

FPGA Design Framework Combined with Commercial VLSI CAD

Qian ZHAO, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI
2013 IEICE transactions on information and systems  
VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons.  ...  We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language.  ...  Acknowledgments This work was supported by the VLSI Design and Education Center (VDEC) of the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design System, Inc., and Mentor Graphics,  ... 
doi:10.1587/transinf.e96.d.1602 fatcat:quem56ufirhpxma7ts23owiz7y

Designing mega-ASICs in nanogate technologies

David E. Lackey, Paul S. Zuchowski, Juergen Koehl
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas  ...  This paper discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach  ...  Placement-based synthesis tool flows for early [1] and late timing closure [4] merged the operation of gate placement (where interconnect timing estimates can be highly accurate) with synthesis (where  ... 
doi:10.1145/775832.776029 dblp:conf/dac/LackeyZK03 fatcat:3zyqburjkrcmpmwvmemgjnmwiu

Designing mega-ASICs in nanogate technologies

David E. Lackey, Paul S. Zuchowski, Juergen Koehl
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas  ...  This paper discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach  ...  Placement-based synthesis tool flows for early [1] and late timing closure [4] merged the operation of gate placement (where interconnect timing estimates can be highly accurate) with synthesis (where  ... 
doi:10.1145/776028.776029 fatcat:ba4ii7i3wrfl5i77f262ebd55y

UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)

Fateh Boutekkouk, Mohammed Benmohammed, Sebastien Bilavarn, Michel Auguin
2009 Journal of Object Technology  
At each level, the design can be described in the form of a behavioral, a structural model, or a physical model.  ...  The final destination of the various parts of the design are decided at the partitioning stage. Two separate design flows start concurrently for the software and hardware.  ...  SOC: System On a Chip. ERS. Embedded Real time Systems. ES. Embedded Systems. WCP. Wireless Communication Protocols. PBD: Platform-Based Design. MDA: Model Driven Architecture.  ... 
doi:10.5381/jot.2009.8.1.a1 fatcat:coirvylxd5amzmiwtz6ymxi6l4
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