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Deterministic clock gating for microprocessor power reduction

Hai Li, S. Bhunia, Y. Chen, T.N. Vijaykumar, K. Roy
The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.  
This paper introduces deterministic clock gating (DCG) based on the key observation that for many of the stages in a modern pipeline, a circuit block's usage in a specific cycle in the near future is deterministically  ...  However, no non-predictive methodologies are available in the literature for efficient clock gating.  ...  Deterministic clock gating Principle of clock gating The clock network in a microprocessor feeds clock to sequential elements like flops and latches, and to dynamic logic gates, which are used in high-performance  ... 
doi:10.1109/hpca.2003.1183529 dblp:conf/hpca/LiBCVR03 fatcat:kvdcfrmcsjew5fwd23bd3fdrje

DCG: deterministic clock-gating for low-power microprocessor design

Hai Li, S. Bhunia, Yiran Chen, K. Roy, T.N. Vijaykumar
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Because clock power can be significant in high-performance processors, we propose a deterministic clock-gating (DCG) technique which effectively reduces clock power.  ...  Index Terms-Deterministic clock-gating (DCG), superscalar microarchitecture.  ...  However, the approach is not effective for general-purpose microprocessor pipelines. III. DETERMINISTIC CLOCK GATING A.  ... 
doi:10.1109/tvlsi.2004.824307 fatcat:fz5iyk3qefettiwewfq4o4wmpy

DL Stefan Rusu Instructs SSCS-Beijing on trends and Challenges in Server-Class Microprocessor Design [People

Stefan Rusu
2010 IEEE Solid-State Circuits Magazine  
Summary Moore's law has fueled the worldwide technology revolution for over 40 years  ...  Figure 3 shows the leakage reduction benefi ts of these respective power gating techniques.  ...  FIGURE 3 : 3 All blocks disabled for yield recovery are power gated to minimize their power consumption.  ... 
doi:10.1109/mssc.2010.938326 fatcat:r6s4ombtvve7jebt7mgamkfm6a

Guest Editorial

C. Piguet, V. Narayanan
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The next paper, DCG: Deterministic Clock Gating For Low-Power Microprocessor Design, by Li et al. presents the application of clock gating to microprocessors.  ...  accesses, achieving significant reduction in execution time and power consumption for multimedia applications.  ... 
doi:10.1109/tvlsi.2004.827390 fatcat:icdgxpr7ufe2rogux4n43mdk2i

Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors

Yiran Chen, K. Roy, Cheng-Kok Koh
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we propose an integrated architectural and physical planning approach to minimize the current surge in high-performance clock-gated microprocessors.  ...  We also show that our approach does not increase the clock period for 0.18-m technology and beyond.  ...  This paper targets the reduction of current surge in clock-gated microprocessors. Clock-gating technology is extensively adopted in high performance microprocessor design.  ... 
doi:10.1109/tvlsi.2004.840404 fatcat:6r7r5dq7ajd6rc3dayojmu2nbi

Automatic Low Power Optimizations during ADL-driven ASIP Design

A. Chattopadhyay, D. Kammler, E. Witte, O. Schliebusch, H. Ishebabi, B. Geukes, R. Leupers, G. Ascheid, H. Meyr
2006 2006 International Symposium on VLSI Design, Automation and Test  
The contribution of this paper any incurred overheadfor area and speed. is to present: * A generic ADL-based clock gating methodology * A deterministic, low-complexity clock gating algorithm for 1-4244  ...  Traditionally, RTL-based clock gating is performed manually.  ...  Since, we derive the gating [ 7...... Deterministic Clock Gating for Microprocessor Power Reduction.  ... 
doi:10.1109/vdat.2006.258140 fatcat:ntckq22pnraqdpekaxsieat7ey

Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors

Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
We propose an integrated architectural/physical planning approach to reduce the power supply noise due to current surge in high performance, general-purpose, clock-gated microprocessors.  ...  The degradation in IPC (Instruction Per Cycle) due to the selection logic and issue width scaling is only 1.86e-7 (without increasing clock cycle period) in 0.18µm technology.  ...  performance, general-purpose, clock-gated microprocessors.  ... 
doi:10.1145/871506.871563 dblp:conf/islped/ChenRK03 fatcat:snhks7a24jepjgbggv45c66fji

Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors

Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
We propose an integrated architectural/physical planning approach to reduce the power supply noise due to current surge in high performance, general-purpose, clock-gated microprocessors.  ...  The degradation in IPC (Instruction Per Cycle) due to the selection logic and issue width scaling is only 1.86e-7 (without increasing clock cycle period) in 0.18µm technology.  ...  performance, general-purpose, clock-gated microprocessors.  ... 
doi:10.1145/871559.871563 fatcat:yfms23yhfbblrfh37zi3mqilhi

"Timing closure by design," a high frequency microprocessor design methodology

S. Posluszny, K. Lee, D. Meltzer, K. Nowka, J. Park, J. Peter, J. Silberman, O. Takahashi, P. Villarrubia, N. Aoki, D. Boerstler, P. Coulman (+5 others)
2000 Proceedings of the 37th conference on Design automation - DAC '00  
This paper presents a design methodology emphasizing early and quick timing closure for high frequency microprocessor designs.  ...  Characteristics of "Timing Closure by Design" are 1) logic partitioned on timing boundaries, 2) predictable control structures (PLAs), 3) static interfaces for dynamic circuits, 4) low skew clock distribution  ...  The clock tree, grid and twig wires were treated as blockages for the power grid generator and global routing. Figure 4 illustrates the clock distribution, showing the Htree, grid and twig wires.  ... 
doi:10.1145/337292.337749 dblp:conf/dac/PoslusznyABCDFHKKLMNPPSTV00 fatcat:s7noxkmoyrhwpljfqll7pwqdka

Technology Scaling And Low Power Design Techniques

T.Esther Rani, Rameshwar Rao
2012 CVR Journal of Science and Technology  
The demand for power-sensitive design has grown significantly in recent years due to growth in portable applications. The need for power-efficient design techniques is increasing.  ...  In this paper, different circuit design techniques both static and dynamic are discussed that reduce the power consumption.  ...  An architecture-level technique called deterministic clock gating (DCG) is also proposed.  ... 
doi:10.32377/cvrjst0207 fatcat:nttg4ogx7rbzndlxc366a7r2nq

Sub-90nm technologies

Tanay Karnik, Shekhar Borkar, Vivek De
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations.  ...  Design practice will have to change from deterministic design to probabilistic and statistical design.  ...  Low swing clock distribution to reduce clock power will be useful, provided that jitter and skew issues at low Vcc can be managed [9] .  ... 
doi:10.1145/774572.774602 dblp:conf/iccad/KarnikBD02 fatcat:5dbe625kd5d7rlxd2c7fhcbqti

Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors

Nasir Mohyuddin, Kimish Patel, Massoud Pedram
2009 2009 IEEE International Conference on Computer Design  
In this paper we present deterministic clock gating schemes for various micro architectural blocks of a modern out-of-order superscalar processor.  ...  The baseline Pipelined Functional unit Clock Gating (PFCG), presented for evaluation purpose only, disables the clock on idle stages and thus results in 13.93% chip-wide energy saving.  ...  CONCLUSION We presented a clock gating scheme that deterministically clock gates the functional units in modern out-of-order superscalar processors to save power.  ... 
doi:10.1109/iccd.2009.5413158 dblp:conf/iccd/MohyuddinPP09 fatcat:g7j7unooezgy3cif2ei6yhehru

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

P. Muller, Y. Leblebici, M. Emsley, M. Unlu, A. Tajalli, M. Atarodi
2006 Proceedings of ESSCIRC  
Measurement results of the manufactured design show operation at data rates exceeding 2.5-Gbps/channel for the detector, the amplification and the clock and data recovery circuits.  ...  This proof of concept is the first step towards design optimized, completely integrated, multi-channel optical receivers for high-bandwidth short-distance chip-to-chip interconnects. I.  ...  In each channel, a clock in sync with the incoming data is obtained at the output of a gated current-controlled oscillator (GCCO).  ... 
doi:10.1109/esscir.2006.307494 fatcat:76f77nbz6ndxnkupojufyqum7u

Performance Enhancement Of 8 Bit Risc Architecture

Pratik Katwate, Sanjay Pardeshi, Vardhman Tiwatane
2018 Zenodo  
In this paper we have selected PIC16A84 processor as base platform for the enhancement of its features. Selected processor is based on the 8bit RISC platform.  ...  This will lead to reduction of power consumption. Total Power Consumption for Enhanced Core: 83.94 mW Max Clock frequency: 29.95 MHz V. CONCLUSION  ...  Today's microprocessors are so much powerful as well as power efficient too.  ... 
doi:10.5281/zenodo.1413404 fatcat:wmqmjwhndjbqbj3foqgdofq2rm

Adaptive Clock Gating Technique for Low Power IP Core in SoC Design

Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimin Zhang, Jun Wang
2007 2007 IEEE International Symposium on Circuits and Systems  
Clock gating is a well-known technique to reduce chip dynamic power.  ...  Based on the analysis of the Intellectual Property (IP) core model, an adaptive clock gating (ACG) technique which can be easily realized is introduced for the low power IP core design.  ...  Considering all the clock signals, the total clock power is usually a substantial 30-35% of the microprocessor power [2] . Clock gating is an effective technique to reduce dynamic power [3] .  ... 
doi:10.1109/iscas.2007.378591 dblp:conf/iscas/ChangZZZW07 fatcat:v2myxhdxcvcpngonhgwim4thpa
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