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E3: Energy-Efficient Microservices on SmartNIC-Accelerated Servers

Ming Liu, Simon Peter, Arvind Krishnamurthy, Phitchaya Mangpo Phothilimthana
2019 USENIX Annual Technical Conference  
We investigate the use of SmartNIC-accelerated servers to execute microservice-based applications in the data center.  ...  We present E3, a microservice execution platform for SmartNIC-accelerated servers.  ...  We would like to thank the anonymous reviewers and our shepherd, Ada Gavrilovska, for their comments and feedback.  ... 
dblp:conf/usenix/LiuPKP19 fatcat:dlnke6vzrzh7fl2lrg5bcks42q

λ-NIC: Interactive Serverless Compute on Programmable SmartNICs [article]

Sean Choi, Muhammad Shahbaz, Balaji Prabhakar, Mendel Rosenblum
2019 arXiv   pre-print
run thousands of lambdas on a single NIC with strict tail-latency guarantees.  ...  To ease development and deployment of lambdas, λ-NIC exposes an event-based programming abstraction, Match+Lambda, and a machine model that allows developers to compose and execute lambdas on SmartNICs  ...  However, modern SmartNICs, more speci cally ASIC-based NICs, consist of hundreds of RISC processors (i.e., NPUs) [11] , each with their local instruction store and memory. ese SmartNICs are more exible  ... 
arXiv:1909.11958v1 fatcat:c3xdjz2jojdsldvhvhl5cdwfge

P4-CoDel: Experiences on Programmable Data Plane Hardware [article]

Ralf Kundel, Amr Rizk, Jeremias Blendin, Boris Koldehofe, Rhaban Hark, Ralf Steinmetz
2021 arXiv   pre-print
Active Queue Management (AQM) algorithms such as CoDel or PIE, designed for the use on software based hosts, offer a flow agnostic remedy to Bufferbloat by controlling the queue filling and hence the latency  ...  While legacy software algorithms can be easily compiled onto almost any processing architecture, this is not generally true for AQM on programmable data plane hardware, i.e., programmable packet processors  ...  Furthermore, we thank our colleagues and reviewers for their valuable input and feedback.  ... 
arXiv:2010.04528v2 fatcat:4k6zr2wx3jfxnmf43jt5o7a67u

sRDMA - Efficient NIC-based Authentication and Encryption for Remote Direct Memory Access

Konstantin Taranov, Benjamin Rothenberger, Adrian Perrig, Torsten Hoefler
2020 USENIX Annual Technical Conference  
State-of-the-art remote direct memory access (RDMA) technologies have shown to be vulnerable against attacks by innetwork adversaries, as they provide only a weak form of protection by including access  ...  Additionally, we provide an implementation for sRDMA using programmable network adapters.  ...  ., especially Fazil Osman, for the donation of two SmartNICs as well as continuous support.  ... 
dblp:conf/usenix/TaranovRPH20 fatcat:a72qpcbe2bfwdjohibpqzr4fmu

Introducing SmartNICs in Server-based Data Plane Processing: the DDoS Mitigation Use Case

Sebastiano Miano, Roberto Doriguzzi-Corin, Fulvio Risso, Domenico Siracusa, Raffaele Sommese
2019 IEEE Access  
We evaluate the performance in different combinations of host and SmartNIC-based mitigation, showing that offloading part of the DDoS network function in the SmartNIC can indeed optimize the packet processing  ...  their usage for a specific use case, namely, the mitigation of Distributed Denial of Service (DDoS) attacks.  ...  For instance, an effective SmartNIC-based solution for DDoS attacks may require the presence of a DDoS-aware load balancer that distributes incoming datacenter traffic in a way to reduce the amount of  ... 
doi:10.1109/access.2019.2933491 fatcat:pu7lz7gk5rdvzgc5xrvqffszqy

Azure Accelerated Networking: SmartNICs in the Public Cloud

Daniel Firestone, Andrew Putnam, Sambrama Mundkur, Derek Chiou, Alireza Dabagh, Mike Andrewartha, Hari Angepat, Vivek Bhanu, Adrian M. Caulfield, Eric S. Chung, Harish Kumar Chandrappa, Somesh Chaturmohta (+20 others)
2018 Symposium on Networked Systems Design and Implementation  
to the Proceedings of the 15th USENIX Symposium on Networked Systems Design and Implementation is sponsored by USENIX.  ...  This paper is included in the Proceedings of the 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI '18).  ...  We thank the entire Azure Networking, Server Infrastructure, and Compute teams for their support in developing, iterating on, and deploying SmartNICs and the Accelerated Networking service.  ... 
dblp:conf/nsdi/FirestonePMCDAA18 fatcat:gx7eaiwfvzhnxjfbyap3p5bcue

Live in the Express Lane

Patrick Jahnke, Vincent Riesop, Pierre-Louis Roman, Pavel Chuprikov, Patrick Eugster
2021 USENIX Annual Technical Conference  
processors and its own memory to buffer packets. The number X-Lane uses the IRQ-based approach to optimize delivery of flow processors used for X-Lane can be scaled on demand timing.  ...  ’s NFP-4000-based smartNICs [8]; just their internal timeouts for the best possible performance. § 5 Definition and implementation of two example asyn- Note, purely bandwidth-oriented  ... 
dblp:conf/usenix/JahnkeRRCE21 fatcat:aoi3x635yjdl5bjnv5m5qo6atm

CEAZ: Accelerating Parallel I/O Via Hardware-Algorithm Co-Designed Adaptive Lossy Compression [article]

Chengming Zhang, Sian Jin, Tong Geng, Jiannan Tian, Ang Li, Dingwen Tao
2021 arXiv   pre-print
However, little work has been done for effectively offloading lossy compression onto FPGA-based SmartNICs to reduce the compression overhead.  ...  Experiments show that CEAZ outperforms the second-best FPGA-based lossy compressor by 2X of throughput and 9.6X of ratio.  ...  Note that similar to the FPGA-based SmartNIC, the emerging Data Processing Unit (DPUs) [10]-a class of programmable processor-based SmartNIC can also offload and improve application performance for communications  ... 
arXiv:2106.13306v2 fatcat:42fvquu3trcgxncxwdl5izksra

HeteroSketch: Coordinating Network-wide Monitoring in Heterogeneous and Dynamic Networks

Anup Agarwal, Zaoxing Liu, Srinivasan Seshan
2022 Symposium on Networked Systems Design and Implementation  
Recent developments in sketch-based monitoring techniques and the deployment opportunities arising from the increasing programmability of network elements (e.g., programmable switches, Smart-NICs, and  ...  We present HeteroSketch, a framework that consists of two main components: (1) a profiling tool that automatically quantifies the capabilities of arbitrary hardware by predicting their performance for  ...  We thank the anonymous reviewers for their valuable feedback. We would like to thank Hun Namkung, Pouya Haghi, Anqi Guo, Zhipeng Zhao, and Nirav Atre for assistance with hardware implementations.  ... 
dblp:conf/nsdi/AgarwalLS22 fatcat:zujyxxljgrbo5mdhrxjwxagy7q

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Prateek Shantharama, Akhilesh S. Thyagaturu, Martin Reisslein
2020 IEEE Access  
The processor supports a 32 bit base IS capable of multiply and divide operations.  ...  a: BASE FREQUENCY The base frequency [135] is the normal CPU operational frequency suggested by the manufacturer to guarantee the CPU performance characteristics in terms of number of operations per  ... 
doi:10.1109/access.2020.3008250 fatcat:kv4znpypqbatfk2m3lpzvzb2nu

The Programmable Data Plane

Oliver Michel, Roberto Bifulco, Gábor Rétvári, Stefan Schmid
2021 ACM Computing Surveys  
for future research.  ...  We elaborate on the trends that led to the emergence of this technology and highlight the most important pointers from the literature, casting different taxonomies for the field, and identifying avenues  ...  We expect to see more host-based services, such as firewalls, L7 gateways, or hypervisor-based load balancing being offloaded to SmartNICs.  ... 
doi:10.1145/3447868 fatcat:hafeovivhfgmpecqzrinsbfmnq

hXDP: Efficient Software Packet Processing on FPGA NICs [article]

Marco Spaziani Brunella, Giacomo Belocchi, Marco Bonola, Salvatore Pontarelli, Giuseppe Siracusano, Giuseppe Bianchi, Aniello Cammarano, Alessandro Palumbo, Luca Petrucci, Roberto Bifulco
2020 arXiv   pre-print
The iterative execution model of eBPF is not a good fit for FPGA accelerators.  ...  Despite these modest requirements, it achieves the packet processing throughput of a high-end CPU core and provides a 10x lower packet forwarding latency.  ...  of this paper.  ... 
arXiv:2010.14145v1 fatcat:zez2kdjypff5fd4ptrwkbujh5a

Clio: A Hardware-Software Co-Designed Disaggregated Memory System [article]

Zhiyuan Guo, Yizhou Shan, Xuhao Luo, Yutong Huang, Yiying Zhang
2022 arXiv   pre-print
It has 1.1x to 3.4x energy saving compared to CPU-based and SmartNIC-based disaggregated memory systems and is 2.7x faster than software-based SmartNIC solutions.  ...  Our FPGA prototype of Clio demonstrates that each memory node can achieve 100 Gbps throughput and an end-to-end latency of 2.5 us at median and 3.2us at the 99th percentile.  ...  of this paper.  ... 
arXiv:2108.03492v3 fatcat:oh23q256dzao7jroxayuexvbuq

Elastic RSS

Alexander Rucker, Muhammad Shahbaz, Tushar Swamy, Kunle Olukotun
2019 Proceedings of the 3rd Asia-Pacific Workshop on Networking 2019 - APNet '19  
, high throughput, and CPU e ciency.  ...  However, these techniques are either too in exible (randomly steering tra c at the NIC) or slow (bottlenecked by a central CPU-based scheduler).  ...  ACKNOWLEDGMENTS We thank members of the Pervasive Parallelism Lab, Neeraja Yadwadkar, and the anonymous APNet reviewers for their valuable feedback that helped improve the quality of this paper.  ... 
doi:10.1145/3343180.3343184 dblp:conf/apnet/RuckerSSO19 fatcat:uzrlbzjzxjfrhlpjluht2ahyha

P4DB – The Case for In-Network OLTP (Extended Technical Report) [article]

Matthias Jasny, Lasse Thostrup, Tobias Ziegler, Carsten Binnig
2022 arXiv   pre-print
In this paper we present a new approach for distributed DBMSs called P4DB, that uses a programmable switch to accelerate OLTP workloads.  ...  The main idea of P4DB is that it implements a transaction processing engine on top of a P4-programmable switch.  ...  We thank Intel for their valuable technical support.  ... 
arXiv:2206.00623v1 fatcat:keej65bawfdnvctohm5drknmgq
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