Filters








2,152 Hits in 2.3 sec

Time- and frequency-domain transient signal analysis for defect detection in CMOS digital ICs

J.F. Plusquellic, D.M. Chiarulli, S.P. Levitan
1999 IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications  
These variations are shown to exist in both the time domain and frequency domain for CMOS open-drain and bridging defects, located both on and off sensitized paths.  ...  Index Terms-CMOS defects, digital device testing, frequency domain, parametric, transient response.  ...  IDDQ has been shown to be an effective diagnostic technique for CMOS bridging defects, but is not applicable to all types of CMOS defects [13] , [14] .  ... 
doi:10.1109/81.802843 fatcat:jsssyogryvf5vhd2re6p274ssm

Design-for-testability techniques for detecting delay faults in CMOS/BiCMOS logic families

M. Ahmadi, K. Raahemifar
2000 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
It is shown that by detecting delayed time response in a transistor circuit, two types of faults are detected: 1) faults which cause delayed transitions at the output node due to some open defects and  ...  Index Terms-Concurrent testing, delay fault and stuck open fault testing, design for testability, fully testable CMOS circuit, VLSI testing. .  ...  Miller, Dean of Engineering at the University of Victoria, Canada, for his constructive and valuable comments.  ... 
doi:10.1109/82.885134 fatcat:erlhh6kkmbaanlvljxhhhsgtki

Single-ended SRAM with high test coverage and short test time

Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao
2000 IEEE Journal of Solid-State Circuits  
The goals of low power, high quality control, and short test time of the full CMOS SRAM can be achieved. Index Terms-High test coverage, IFA-9, retention fault, singleended cell, SRAM.  ...  In this paper, we present the configuration and test strategy of a single-ended, six-transistor SRAM. The benefits of short test time, no retention test, and high test coverage are verified.  ...  The retention time depends on the capacitance of the node and the leakage current from the defective node to .  ... 
doi:10.1109/4.818928 fatcat:jfmtudaejffdpgiceqd2b3gmqu

[Invite Paper] High Accuracy High Spatial Resolution and Real-Time CMOS Proximity Capacitance Image Sensor Technology and its Applications

Rihito Kuroda, Masahiro Yamamoto, Yuki Sugama, Yoshiaki Watanabe, Manabu Suzuki, Tetsuya Goto, Toshiro Yasuda, Shinichi Murakami, Yayoi Yokomichi, Hiroshi Hamori, Shigetoshi Sugawa
2021 ITE Transactions on Media Technology and Applications  
The examples of capacitance imaging using the fabricated CMOS proximity capacitance image sensor are demonstrated.  ...  In this paper, the proximity capacitance CMOS image sensor technology with high detection accuracy, high spatial resolution and real-time detection and its applications are presented.  ...  Acknowledgment The authors would like to thank LAPIS Semiconductor for fabrication of the chip, and Y. Itoya and R. Yamazaki for the measurements of capacitance images of signatures.  ... 
doi:10.3169/mta.9.122 fatcat:brrskk6wdzapzkywnizfkzmq2m

Guest editors' introduction: defect-oriented testing in the deep-submicron era

J. Segura, P. Maxwell
2002 IEEE Design & Test of Computers  
Defect-oriented test strategies first analyze defect properties, and then determine the best test technique for detection.  ...  The lack of solutions offered by logic fault models was especially severe for high-reliability applications.  ...  Peter Maxwell Agilent Technologies detection of open defects, the work focused mainly on hard opens (defects causing a complete interconnect isolation).  ... 
doi:10.1109/mdt.2002.1033786 fatcat:pypu7pvts5hexkoo7bsfjy4zbq

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias

Hector Villacorta, Jose Garcia-Gervacio, Victor Champac, Sebastia Bota, Jaime Martinez, Jaume Segura
2013 2013 14th Latin American Test Workshop - LATW  
The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage that gives a more realistic measure of the degree of detection of the defect.  ...  Because of this, in this work a Statistical Timing Analysis Framework (STAF) is used to analyze the possibilities of detection of bridge defect using a delay based test.  ...  Jaume Segura and Sebastia Bota acknowledge support from the Spanish Ministry of Economics and Com petitivity and the Regional European Development fu nds (FEDER) from EU under project TEC2011-25017.  ... 
doi:10.1109/latw.2013.6562671 dblp:conf/latw/VillacortaGCBMS13 fatcat:ri2nviahbrhrrkncrpd7wjdogq

A versatile built-in cmos sensing device for digital circuit parametric test

M.S. Dragic, M. Margala
2003 IEEE Transactions on Instrumentation and Measurement  
Our analysis shows excellent detection capabilities of non-catastrophic short and open defects.  ...  The presented sensor is scalable and practical embedded solution for high-frequency parametric I DDQ test of standard CMOS digital circuits.  ...  ACKNOWLEDGEMENT The authors want to thank Canadian Microelectronics Corporation for their support in fabrication of the chips.  ... 
doi:10.1109/tim.2003.818725 fatcat:wf74eubor5hc3fnn7ydpdnr4ru

Online Fabric Defect Inspection Using Smart Visual Sensors

Yundong Li, Jingxuan Ai, Changqing Sun
2013 Sensors  
The following are considered in dealing with broken-end defects caused by a single yarn: first, a smart visual sensor is composed of a powerful DSP processor and a 2-megapixel high definition image sensor  ...  Traditionally, fabric inspection to assure textile quality is done by humans, however, in the past years, researchers have paid attention to PC-based automatic inspection systems to improve the detection  ...  Traditionally, defects are detected by human eyes, but the efficiency of the manual method is low because of eye fatigue.  ... 
doi:10.3390/s130404659 pmid:23571669 pmcid:PMC3673105 fatcat:2u5ucxi3ybc6hduewzuptflstq

Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs

J.L. Rossello, C. de Benito, S.A. Bota, J. Segura
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
In this work we investigate the merits of this technique for future technologies where variation is predicted to increase, analyzing the possibilities of detecting resistive shorts and opens.  ...  Several works have shown the relative increase of resistive defects (both opens and shorts), and that they mainly affect circuit timing rather than impacting its static DC behavior.  ...  Note that the goal of this analysis is not to guarantee a detection of a given short in a circuit by using delay testing, but to provide a comparative analysis to determine the benefit of lowering the  ... 
doi:10.1109/date.2007.364472 fatcat:q3p3domynbhozjoj6logqlibcy

Surface Defect Detection and Classification Based on Statistical Filter and Decision Tree

Habibullah Akbar, Nanna Suryana, Fikri Akbar
2013 Journal of clean energy technologies  
Industrial quality inspection is a major issue due to the growing of market competitiveness which requires the product to be checked in terms of online defect detection.  ...  This study presents an inspection scheme to detect defect in plain fabric based on statistical filter and geometrical features on CMOS-based image input.  ...  Until now, there are numerous proposed surface defect detection method based on statistical analysis. The method includes spatial and frequency domain processing.  ... 
doi:10.7763/ijcte.2013.v5.794 fatcat:jb3ar62nbjaufc5x7ln32tkbwq

Analyzing the memory effect of resistive open in CMOS random logic

M. Renovell, M. Comte, I. Polian, P. Engelke, B. Becker
2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.  
It is also shown that, due to the memory effect detection of the open by a given vector Ti depends on all the vectors that have been applied to the circuit before Ti.  ...  An electrical analysis of this memory effect is presented.  ...  Tn is such that the transitions created by the 2 vectors {T n-1 , T n } are able to detect the resistive open on node n 4 .  ... 
doi:10.1109/dtis.2006.1708691 fatcat:3ihneagq45g75gacdhjjwko4mu

Testability enhancement of a basic set of CMOS cells

M. Rullán, J. Oliver, C. Ferrer, F. C. Blom
1994 Quality and Reliability Engineering International  
We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect).  ...  The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrbnica (CNM) and obtain a highly testable cell library.  ...  The following types of defects have been reported as main causes of CMOS IC failure: bridging, open drain or source, open gate, transmission gate opens, gate oxide shorts, parasitic transistor leakage  ... 
doi:10.1002/qre.4680100406 fatcat:lyysn4nwkvew3abz5k56zt2ive

Built-in current sensor for ΔI/sub DDQ/ testing

J.R. Vazquez, J. Pineda de Gyvez
2004 IEEE Journal of Solid-State Circuits  
If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the "Taverne" license above, please follow below link for the End User Agreement: www.tue.nl/taverne  ...  Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of  ...  INTRODUCTION F OR ABOUT 25 years, testing of CMOS digital circuits has been recognized as an advantageous methodology to detect defects missed by conventional logic testing.  ... 
doi:10.1109/jssc.2003.822900 fatcat:6umctbmcinaqtkup5lgkmbt6hq

On the issues of oscillation test methodology

M.W.-T. Wong
2000 IEEE Transactions on Instrumentation and Measurement  
This paper presents a detailed case study of using the oscillation test methodology to test an active low pass filter. We highlight some of the difficulties and shortcomings of this testing approach.  ...  The two approaches are: • If the layout is available, the defect size and frequency distribution of the manufacturing process can be modeled using a Monte Carlo defect simulator that places missing or  ...  Moreover, open fault is modeled by a 20 M resistor while short fault is modeled by a 10 resistor for simulations.  ... 
doi:10.1109/19.843056 fatcat:r6wgo3iq3vfkfkkgpckpgxeata

Localization and Electrical Characterization of Interconnect Open Defects

R. Rodriguez-Montaes, D. Arumi, J. Figueras, W. Beverloo, D.K. de Vries, S. Eichenberger, P.A.J. Volf
2010 IEEE transactions on semiconductor manufacturing  
A technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented.  ...  Experimental results show a good agreement between the predicted location of the open and its real location, found by optical beam induced resistance change inspection.  ...  Furthermore, the range of resistances detected by the proposed method has been analyzed for the previous technology nodes.  ... 
doi:10.1109/tsm.2009.2039187 fatcat:5bpdp3qoafewrbr3mbxkoyvydm
« Previous Showing results 1 — 15 out of 2,152 results