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A novel macroblock-level filtering upsampling architecture for H.264/AVC scalable extension

Thaísa Leal da Silva, Luís Alberto da Silva Cruz, Luciano Volcan Agostini
2010 Proceedings of the 23rd symposium on Integrated circuits and system design - SBCCI '10  
Table I presents the synthesis results of the architecture designed for Altera Cyclone III and Stratix IV FPGAs.  ...  This high throughput is function of the efficient technology used in the FPGAs and it is also function of the low number of cycles that the designed architecture needs to process each VGA frame.  ... 
doi:10.1145/1854153.1854194 dblp:conf/sbcci/SilvaCA10 fatcat:dl4e6zlajbc6zn56i3fanfgy2y

Author index

2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
Design for H.264 Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis Graphic processors to speed up simulations for the design of high performance solar receptors Design and Implementation  ...  in User-Guided High-Level Synthesis Parallelizing HMMER for hardware accel- eration on FPGAs 0/1 Knapsack on Hardware: A Complete Solution A Compact Fading Channel Simulator Us- ing Timing-Driven  ... 
doi:10.1109/asap.2007.4459300 fatcat:lbxlom2lkrf2jf3q5c56uwiuea

An FPGA-Based Implementation of Spatio-Temporal Object Segmentation

Kumara Ratnayake, Aishy Amer
2006 2006 International Conference on Image Processing  
This paper proposes a robust real-time, scalable and modular Field Programmable Gate Array (FPGA) based implementation of a spatiotemporal segmentation of video objects.  ...  The design was successfully simulated, synthesized and tested for real-time performance on an actual hardware platform which consists of a frame grabber with a user programmable FPGA -Xilinx Virtex-II  ...  Spatio-Temporal Thresholding Architecture The high-level architecture designed for the spatio-temporal thresholding is shown in Fig. 3 .  ... 
doi:10.1109/icip.2006.312920 dblp:conf/icip/RatnayakeA06 fatcat:bqeuzbhcmva5lk62emi2heq4ze

A Systematic Method for Hardware Software Codesign using Vivado HLS

2019 International journal of recent technology and engineering  
This paper aims to provide increased productivity for designing, integrating and implementing systems using xilinx vivado design suite.  ...  Improved productivity results are indicated through simulation, synthesis, implementation, bitstream generation.  ...  Very High Level Synthesis for Image Processing Applications (YanjingBI, 2016) this paper aims to produce effective model for FPGA designs in Matlab environment by using very high level synthesis  ... 
doi:10.35940/ijrte.d7008.118419 fatcat:4zfv2o6c75amjeadsgwrowsirm

2018 IndexIEEE Embedded Systems LettersVol. 10

2018 IEEE Embedded Systems Letters  
., +, LES Sep. 2018 69-72 Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.  ...  ., +, LES Sep. 2018 77-80 Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.  ... 
doi:10.1109/les.2018.2875502 fatcat:do7ufineb5c4dip4gh5lcnvozi

CNN2Gate: Toward Designing a General Framework for Implementation of Convolutional Neural Networks on FPGA [article]

Alireza Ghaffari, Yvon Savaria
2020 arXiv   pre-print
Because of the research efforts put into topics such as architecture, synthesis and optimization, some new challenges are arising to integrate such hardware solutions to high-level machine learning software  ...  CNN2Gate performs design-space exploration using a reinforcement learning agent and fits the design on different FPGAs with limited logic resources automatically.  ...  OpenCL-based high-level synthesis of CNNs OpenCL High-level Synthesis on FPGAs OpenCL can be used to write programs that can be executed across heterogeneous platforms.  ... 
arXiv:2004.04641v2 fatcat:zu6dxff2urg57ejzrn4ac2jkha

High-Level Design of Portable and Scalable FPGA Accelerators [article]

Markus Weinhardt, Rainer Höckmann, Thomas Kinder
2014 arXiv   pre-print
This paper presents our approach for making FPGA accelerators accessible to software (SW) programmers.  ...  We report on our current SAccO platform (Scalable Accelerator platform Osnabr\"uck) and the planned project extending this platform.  ...  Due to recent advances in high-level synthesis (HLS) [4] it now becomes feasible to replace the VHDL components by HLS-generated HW designs. This will be explored in the course of this new project.  ... 
arXiv:1408.5383v1 fatcat:u3y2q7a4yzclvdvnwt7ulymlrm

Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing [article]

Akshay Dua, Yixing Li, Fengbo Ren
2020 arXiv   pre-print
This paper presents Systolic-CNN, an OpenCL-defined scalable, run-time-flexible FPGA accelerator architecture, optimized for accelerating the inference of various convolutional neural networks (CNNs) in  ...  Systolic-CNN adopts a highly pipelined and paralleled 1-D systolic array architecture, which efficiently explores both spatial and temporal parallelism for accelerating CNN inference on FPGAs.  ...  High-level synthesis (HLS) tools, such as the Intel FPGA SDK for OpenCL, allow function modeling at a much higher level, thus enabling a faster design and verification cycle.  ... 
arXiv:2012.03177v1 fatcat:h5alzshjybhv7kmpmeb46an3qm

A Modified KNN Algorithm for High-Performance Computing on FPGA of Real-Time m-QAM Demodulators

David Marquez-Viloria, Luis Castano-Londono, Neil Guerrero-Gonzalez
2021 Electronics  
This paper presents a parallel implementation of a KNN algorithm focused on the m-QAM demodulators using high-level synthesis for fast prototyping, parameterization, and scalability of the design.  ...  A methodology for scalable and concurrent real-time implementation of highly recurrent algorithms is presented and experimentally validated using the AWS-FPGA.  ...  The KNN was implemented in the FPGA using Vivado HLS (High-Level Synthesis).  ... 
doi:10.3390/electronics10050627 fatcat:txwb5b223zbfpmojn3tuqwpdm4

sFPGA — A scalable switch based FPGA architecture and design methodology

Shakith Fernando, Xiaolei Chen, Yajun Ha
2008 2008 International Conference on Field Programmable Logic and Applications  
In this paper, we propose sFPGA, a scalable FPGA architecture, which is a hybrid between hierarchical interconnection and Network-on-Chip.  ...  A few alternative interconnection network architectures have been proposed for future FPGAs, but they still have several design challenges that need to be addressed.  ...  Section 3 introduces the new scalable FPGA architecture. Section 4 introduces its design methodology using a case study before concluding in Section 5.  ... 
doi:10.1109/fpl.2008.4629914 dblp:conf/fpl/FernandoCH08 fatcat:qyaz2fghhbb4ncruz7y6aqurju

IPPro: FPGA based image processing processor

Fahad Manzoor Siddiqui, Matthew Russell, Burak Bardak, Roger Woods, Karen Rafferty
2014 2014 IEEE Workshop on Signal Processing Systems (SiPS)  
the paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications.  ...  For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set.  ...  In this paper, a high performance and scalable soft-core processor design has been presented.  ... 
doi:10.1109/sips.2014.6986057 dblp:conf/sips/SiddiquiRBWR14 fatcat:udgld6xz7be4jogbdyglzbhehy

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

Dirk Stroobandt, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, Xinyu Niu, Dionisios Pnevmatikatos, Amit Kulkarni, Elias Vansteenkiste, Wayne Luk (+7 others)
2016 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)  
In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental  ...  EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low  ...  At this stage, this model is assumed to be a high-level specification of the platform that will be used for the execution.  ... 
doi:10.1109/recosoc.2016.7533896 dblp:conf/recosoc/StroobandtVCKBC16 fatcat:3hjjgwqrdzf5notzalewyjdybm

Guest Editorial Special Section on Configurable Computing Design—II: Hardware Level Reconfiguration

Toomas P. Plaks
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This is achieved by using double gate transistors technology. In "Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs," Y.  ...  The last paper of this issue brings us back to the configurable architecture of complex application. The paper "System Architecture and Implementation of MIMO Sphere Decoders on FPGA," by X.  ...  His research interests include the design of high-performance application-specific processors, massively parallel computer systems, and reconfigurable architectures in mobile computing and multimedia applications  ... 
doi:10.1109/tvlsi.2007.914084 fatcat:v2hlvtqxgba6rplso6fgafve3a

Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

Yangfan Liu, Peng Liu, Yingtao Jiang, Mei Yang, Kejun Wu, Weidong Wang, Qingdong Yao
2010 International journal of electronics (Print)  
In addition, FPGA-based emulation design typically requires the whole system to be re-synthesised and re-implemented on FPGA when there are any architectural and/or logic changes to be made on the system  ...  However, the scalability of these designs is limited with a single FPGA per board.  ... 
doi:10.1080/00207217.2010.512017 fatcat:qbrf2q4uujdbfisp7oj3rbpojy

Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

Ghislain Roquier, Endri Bezati, Marco Mattavelli
2012 Journal of Electrical and Computer Engineering  
from a unique high-level description of the application, based on the dataflow paradigm, running onto heterogeneous architectures composed by reconfigurable hardware units and multicore processors.  ...  This paper presents a design flow for the hardware and software synthesis of heterogeneous systems allowing to automatically generate hardware and software components as well as appropriate interfaces,  ...  The synthesis is directly obtained from high-level descriptions of both application programs and platform architectures.  ... 
doi:10.1155/2012/484962 fatcat:yylyrvov45go5gdsn2gx4rwj4a
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