Filters








8,401 Hits in 5.0 sec

Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

Jan Van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu
2012 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture  
Programmable RegX Accelerator Architecture comprising fast programmable state machines, simple processing elements and a software-managed L1 cache -Functionality available as a set of single-cycle primitive  ...  of input characteristics Compiler stack PowerEN TM RegX Implementation SOC design in 45-nm SOI, clocked at 2.3 GHz RegX: 15.4 mm 2 (chip size: 410 mm 2 ) Theoretical peak scan rate: 73.6 Gbit/s Measured  ...  Objectives and Challenges Design Objectives A regular-expression accelerator and compiler, supporting 1. thousands of regular expressions 2. high scan rates ~20 Gbit/s 3. millions of active sessions  ... 
doi:10.1109/micro.2012.49 dblp:conf/micro/LunterenHHBSA12 fatcat:p4pt2gkkm5cvpglmacofe5n3d4

Real-time pattern matching with FPGAs

Louis Woods, Jens Teubner, Gustavo Alonso
2011 2011 IEEE 27th International Conference on Data Engineering  
., wire-speed processing and predictable performance. The demonstration is based on a query-to-hardware compiler for complex event patterns that we presented at VLDB 2010 [1] .  ...  We demonstrate a hardware implementation of a complex event processor, built on top of field-programmable gate arrays (FPGAs).  ...  The hardware circuits generated by our compiler are designed to consume arbitrary input data at full wire speed.  ... 
doi:10.1109/icde.2011.5767937 dblp:conf/icde/WoodsTA11 fatcat:z3nlan33rrfcvfnreeffqc66va

Using String Matching for Deep Packet Inspection

Po-Ching Lin, Ying-Dar Lin, Yuan-Cheng Lai, Tsern-Huei Lee
2008 Computer  
Matching expressive pattern specifications with a scalable and efficient design, accelerating the entire packet flow, and string matching with high-level semantics are promising topics for further study  ...  Much work has been done in both algorithm design and hardware implementation to accelerate the inspection, reduce pattern storage space, and efficiently handle regular expressions.  ...  Joao Bispo and his colleagues compared several designs for regular expression matching. 5 Most of these designs can perform regular expression matching on the order of several gigabits per second.  ... 
doi:10.1109/mc.2008.138 fatcat:rreuv55x4vbjdd5dklob75fceu

FEACAN: Front-end acceleration for content-aware network processing

Yaxuan Qi, Kai Wang, Jeffrey Fong, Yibo Xue, Jun Li, Weirong Jiang, Viktor Prasanna
2011 2011 Proceedings IEEE INFOCOM  
FEACAN employs a software-hardware co-design supporting both signature matching and regular expression matching for content-aware network processing.  ...  In this paper, we propose a system-level solution named FEACAN for front-end acceleration of content-aware network processing.  ...  FEACAN has a software-hardware co-designed architecture supporting both signature matching and regular expression matching.  ... 
doi:10.1109/infcom.2011.5935021 dblp:conf/infocom/QiWFXLJP11 fatcat:7ubbxrxtvvfsxflc72enamfptm

IMPROVING THE EFFICIENCY OF A USER-DRIVEN LEARNING SYSTEM WITH RECONFIGURABLE HARDWARE.: APPLICATION TO DNA SPLICING

E. LEMOINE, D. MERCERON, J. SALLANTIN, E. MEPHU NGUIFO
1998 Biocomputing '99  
Their cooperation is thus achieved with an real time interaction speed. The designed system has been partially applied to the recognition of primate splice junctions sites in genetic sequences.  ...  This paper describes a new approach to problem solving by splitting up problem component parts between software and hardware.  ...  Acknowledgments Financial support for this work has been made available by F rench programmes: GDR 1029 Informatique et Genomes and GIP GREG.  ... 
doi:10.1142/9789814447300_0029 fatcat:4sf5rkmgkzd3di2qycywu2dlsq

Co-match

Chao Zhu, Yingke Xie, Mingshu Wang, Jizhong Han, Chengde Han
2009 Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems - ANCS '09  
Second, an FPGA-based coprocessor is developed in order to support fast parallel regular expression matching for multiple flows in hardware.  ...  With this scheme, each packet is only matched against a subset of signatures, bringing about a remarkable improvement of matching speed in software.  ...  To speed up regular expression matching process, many hardware-based approaches have been proposed [7] [8] [9] [10] .  ... 
doi:10.1145/1882486.1882538 dblp:conf/ancs/ZhuXWHH09 fatcat:ycrdqbmjjffjpddx6qnth736eu

An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall [chapter]

John W. Lockwood, Christopher Neely, Christopher Zuver, James Moscola, Sarang Dharmapurikar, David Lim
2003 Lecture Notes in Computer Science  
Packet payloads are scanned for keywords using parallel regular expression matching circuits. Packet headers are compared to rules specified in Ternary Content Addressable Memories (TCAMs).  ...  All packet processing operations were implemented with reconfigurable hardware and fit within a single Xilinx Virtex XCV2000E Field Programmable Gate Array (FPGA).  ...  To implement other high-speed payload scanning circuits, an automated design process was created to generate circuits from a specification of regular expressions [5] .  ... 
doi:10.1007/978-3-540-45234-8_83 fatcat:7h7mkr4gm5cjzjfbaybq7e4fva

Complex event detection at wire speed with FPGAs

Louis Woods, Jens Teubner, Gustavo Alonso
2010 Proceedings of the VLDB Endowment  
To solve this problem, in this paper we present a hardware-based complex event detection system implemented on field-programmable gate arrays (FPGAs).  ...  By inserting the FPGA directly into the data path between the network interface and the CPU, our solution can detect complex events at gigabit wire speed with constant and fully predictable latency, independently  ...  As an example, consider the regular expression A B | B A (which matches either "AB" or "BA").  ... 
doi:10.14778/1920841.1920926 fatcat:24rjccjz6jhtzdq2ztayuqxt5u

Runtime Parameterizable Regular Expression Operators for Databases

Zsolt Istvan, David Sidler, Gustavo Alonso
2016 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)  
In this paper we explore the tradeoff between resource efficiency and expression complexity for an FPGA accelerator targeting string-matching operators (LIKE and REGEXP LIKE in SQL).  ...  On complex regular expressions, the FPGA is faster but needs to be parametrized at runtime to be able to support different queries.  ...  Part of this work has been funded by a grant from the MSR-ETHZ-EPFL Joint Research Center.  ... 
doi:10.1109/fccm.2016.61 dblp:conf/fccm/IstvanSA16 fatcat:5ztxhnnngnduhep2wtyv3yskn4

Introduction to the wire-speed processor and architecture

H. Franke, J. Xenidis, C. Basso, B. M. Bass, S. S. Woodward, J. D. Brown, C. L. Johnson
2010 IBM Journal of Research and Development  
The WSP combines 16 multithreaded IBM PowerPC A cores with special-purpose dedicated accelerators optimized for packet processing, security, pattern matching, compression, Extensible Markup Language (XML  ...  The WSP represents a generic processor architecture in which processing cores, hardware accelerators, and I/O functions are closely coupled in a system on a chip.  ...  He is the author or a coauthor of more than 40 patents and publications.  ... 
doi:10.1147/jrd.2009.2036980 fatcat:p3ogc2zpsjbchbsqylxoire5sa

MXQuery with Hardware Acceleration

Peter M. Fischer, Jens Teubner
2012 2012 IEEE 28th International Conference on Data Engineering  
We demonstrate MXQuery/H, a modified version of MXQuery that uses hardware acceleration to speed up XML processing.  ...  The main goal of this demonstration is to give an interactive example of hardware/software co-design and show how system performance and energy efficiency can be improved by offloading tasks to FPGA hardware  ...  We off-load XML projection to a tailor-made hardware solution and thus leverage one of the particular strengths of FPGA hardware, regular expression matching.  ... 
doi:10.1109/icde.2012.130 dblp:conf/icde/FischerT12 fatcat:6gzizgtfh5btneuhjd645skbgi

A Survey on Hardware Solutions for Signature-Based Security Systems

Serhii Hilgurt
2021 International Workshop on Information Technologies: Theoretical and Applied Problems  
A deep analysis of main directions of security systems hardware acceleration has done. The most promising direction based on the use of FPGA and programmable logic is more closely investigated.  ...  Therefore, many hardware approaches are proposed to accelerate the computational-intensive pattern matching procedure.  ...  In contrast to conventional binary-, ternary-memory provides limited possibility for flexible matching based on regular expression [6] .  ... 
dblp:conf/ittap/Hilgurt21 fatcat:kkdhtsiukve6llvocu42p5j6ku

Compiling PCRE to FPGA for accelerating SNORT IDS

Abhishek Mitra, Walid Najjar, Laxmi Bhuyan
2007 Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems - ANCS '07  
The SNORT IDS system uses the PCRE Engine for regular expression matching on the payload.  ...  Since the software based PCRE engine can match the payload with a single regular expression at a time, and needs to do so for multiple rules in the ruleset, the throughput of the SNORT IDS system dwindles  ...  The interface throughput suffices for wire-speed payload scanning of even the fastest available ethernet interfaces.  ... 
doi:10.1145/1323548.1323571 dblp:conf/ancs/MitraNB07 fatcat:kcus7v7ljre7fbj7budn6zv3nm

Hardware accelerator design for data centers

Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Andrey Ayupov, Steven Burns, Ozcan Ozturk
2015 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
To overcome this problem, customized applicationspecific accelerators are becoming integral parts of modern system on chip (SOC) architectures.  ...  In this paper, we summarize existing hardware accelerators for data centers and discuss the techniques to implement and embed them along with the existing SOCs. 978-1-4673-8388-2/15/$31.00 ©2015 IEEE  ...  Wire-speed processor includes specialized units for common data center operations such as a compression/decompression unit, XML parser unit, cryptography unit, and a regular expression, pattern matching  ... 
doi:10.1109/iccad.2015.7372648 dblp:conf/iccad/YesilOKABO15 fatcat:swlgxlan55ezhcuzifg2hr2fga

The Case for Network Accelerated Query Processing

Alberto Lerner, Rana Hussein, Philippe Cudré-Mauroux
2019 Conference on Innovative Data Systems Research  
The network switches that connect MPP nodes are hard-wired to perform packetforwarding logic only. However, in a recent paradigm shift, network devices are becoming "programmable."  ...  In this paper we explore this programmability to accelerate OLAP queries. We determined that we can offload onto the switch some very common and expensive query patterns.  ...  This project has received funding from the European Research Council (ERC) under the European Unions Horizon 2020 research and innovation programme (grant agreement 683253/GraphInt).  ... 
dblp:conf/cidr/LernerHC19 fatcat:6e3sr6vakfhcxdi7en5pecca2q
« Previous Showing results 1 — 15 out of 8,401 results