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P3Stor: A parallel, durable flash-based SSD for enterprise-scale storage systems

Nong Xiao, ZhiGuang Chen, Fang Liu, MingChe Lai, LongFei An
2011 Science China Information Sciences  
Based on the proposed parallel architecture, we design a lazy flash translation layer (LazyFTL) to manage the address space.  ...  We propose P3Stor, a parallel solid state storage architecture that makes full use of flash memory by utilizing module-and bus-level parallelisms to increase average bandwidth and employing chip-level  ...  Conclusions We have designed a parallel flash-based storage device called P3Stor that makes full use of flash chips. The architecture of P3Stor employs four levels of parallelisms.  ... 
doi:10.1007/s11432-011-4266-z fatcat:4p7rzpljcvekhps7qsjhemtyte

Improving Database Performance Using a Flash-Based Write Cache [chapter]

Yi Ou, Theo Härder
2012 Lecture Notes in Computer Science  
The use of flash memory as a write cache for a database stored on magnetic disks has been so far largely ignored.  ...  In this paper, we explore how flash memory can be efficiently used for this purpose and how such a write cache can be implemented.  ...  Two design decisions are critical to the performance of flash-based caches: -When should a page be admitted into the cache? This is specified by cacheadmission strategies.  ... 
doi:10.1007/978-3-642-29023-7_2 fatcat:ewbvolhocrd67om442eklgthju

DAC: A Device-Aware Cache Management Algorithm for Heterogeneous Mobile Storage Systems

2008 IEICE transactions on information and systems  
and a NAND flash memory.  ...  mobile storage, performance optimization, device-aware cache management, dynamic cache partitioning, workloadaware management Young-Jin Kim received the B.E. degree and the M.E. degree in electrical engineering  ...  In designing the lower level of DAC, we have two cache management policies: 1) The size of each partition should be adjusted so that sequential accesses may be forwarded to either of the two devices earlier  ... 
doi:10.1093/ietisy/e91-d.12.2818 fatcat:sn32thraazeabe3p4nwcwuth7i

Optimizing Flash-based Key-value Cache Systems

Zhaoyan Shen, Feng Chen, Yichen Jia, Zili Shao
2016 USENIX Workshop on Hot Topics in Storage and File Systems  
Leveraging the domain knowledge of key-value caches and the unique device-level properties, we can maximize the efficiency of a key-value cache system on flash devices while minimizing its weakness.  ...  We advocate to reconsider the hardware/software architecture design by directly opening device-level details to key-value cache systems.  ...  Design Overview Our design consists of three main layers (see Figure 1): (1) An enhanced flash-aware key-value cache, which is highly optimized for flash memory storage, runs at the application level  ... 
dblp:conf/hotstorage/ShenCJS16 fatcat:6hblcngj35hkpf7ad2lqumdu24

CacheDedup: In-line Deduplication for Flash Caching

Wenji Li, Gregory Jean-Baptise, Juan Riveros, Giri Narasimhan, Tony Zhang, Ming Zhao
2016 USENIX Conference on File and Storage Technologies  
Flash caching has emerged as a promising solution to the scalability problems of storage systems by using fast flash memory devices as the cache for slower primary storage.  ...  First, it proposes a novel architecture that integrates the caching of data and deduplication metadata (source addresses and fingerprints of the data) and efficiently manages these two components.  ...  thank the anonymous reviewers and our shepherd, Geoff Kuenning, for their thorough reviews and insightful suggestions, and our colleagues at the VISA Research Lab, Dulcardo Arteaga, for his help with the caching  ... 
dblp:conf/fast/LiJRNZZ16 fatcat:3aci5i3znrestmjuq2bzsuq344

An adaptive write buffer management scheme for flash-based SSDs

Guanying Wu, Xubin He, Ben Eckart
2012 ACM Transactions on Storage  
We run trace-driven simulations to verify our design and find that it outperforms other popular flash-aware cache schemes under different workloads.  ...  For instance, compared to a popular flash aware cache algorithm BPLRU, BPAC reduces the number of cache evictions by up to 79.6% and 34% on average.  ...  Two of these important techniques, FTL and flash-aware cache schemes, are described in next two sections.  ... 
doi:10.1145/2093139.2093140 fatcat:44e34txgzja5pd6t3iu3wjuhau

An Efficient Design and Implementation of Multi-level Cache for Database Systems [chapter]

Jiangtao Wang, Zhiliang Guo, Xiaofeng Meng
2015 Lecture Notes in Computer Science  
In this paper, we propose a SSD-based multilevel buffer scheme, called flash-aware second-level cache(FASC), where SSD serves as an extension of the DRAM buffer.  ...  The capacity and performance characteristics of SSD make it well-suited for use as a second-level buffer cache.  ...  In this paper, we propose a flash-aware second-level cache scheme(FASC). The FASC takes flash-based SSD as a non-volatile caching layer for hard disk.  ... 
doi:10.1007/978-3-319-18120-2_10 fatcat:j3iqsluysfft7ivr6kcufhjmga

NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level

Myoungsoo Jung, Ellis Herbert Wilson, David Donofrio, John Shalf, Mahmut Taylan Kandemir
2012 012 IEEE 28th Symposium on Mass Storage Systems and Technologies (MSST)  
However, when designing NAND flash-based devices, making decisions about the optimal system configuration is nontrivial because NAND flash is sensitive to a large number of parameters, and some parameters  ...  mode, 2) the main source of this performance bottleneck is I/O bus activity, not NAND flash activity itself, 3) multi-level-cell NAND flash provides lower I/O bus resource contention than single-level-cell  ...  .), Seung-hwan Song (University of Minnesota), and Yulwon Cho (Stanford University) for technical support/discussion on NAND flash memory technologies.  ... 
doi:10.1109/msst.2012.6232389 dblp:conf/mss/JungWDSK12 fatcat:slw2nvg22jaepiwqwo4h64uwpi

MetaData persistence using storage class memory

Jithin Jose, Mohammad Banikazemi, Wendy Belluomini, Chet Murthy, Dhabaleswar K. Panda
2013 Proceedings of the 1st Workshop on Interactions of NVM/FLASH with Operating Systems and Workloads - INFLOW '13  
Our performance evaluations reveal that SCM aware Flash Cache design could enable persistence with less than 2% degradation in performance.  ...  Similarly, redesigning SolidDB persistence layer using SCM improved the performance by a factor of two.  ...  a factor of two.  ... 
doi:10.1145/2527792.2527800 dblp:conf/sosp/JoseBBMP13 fatcat:gyyc6tmkbrhphb24hvm2jlmyi4

Cache, cache everywhere, flushing all hits down the sink: On exclusivity in multilevel, hybrid caches

Raja Appuswamy, David C. van Moolenbroek, Andrew S. Tanenbaum
2013 2013 IEEE 29th Symposium on Mass Storage Systems and Technologies (MSST)  
Several multilevel storage systems have been designed over the past few years that utilize RAM and flash-based SSDs in concert to cache data resident in HDD-based primary storage.  ...  In doing so, we will first present a comparative evaluation of various techniques that have been proposed to achieve exclusivity in distributed storage caches in the context of a direct-attached, hybrid  ...  To compare these two designs, we implemented sieving-enabled CA-UARC (SE-CA-UARC), and sieving-aware replacement in CA-UARC (SAR-CA-UARC).  ... 
doi:10.1109/msst.2013.6558445 dblp:conf/mss/AppuswamyMT13 fatcat:bet4h646lfbghg4qg2heesq2qm

A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping

Dongchul PARK, Biplob DEBNATH, David H.C. DU
2016 IEICE transactions on information and systems  
In addition, we design a spatial locality-aware caching mechanism and adaptive cache partitioning to further improve CFTL performance.  ...  Since the FTL has a critical impact on the performance and reliability of flash-based storage, a variety of FTLs have been proposed.  ...  To reduce this overhead, we specially design a spatial locality-aware caching mechanism to get extra benefits from the spatial locality in workloads as well as a temporal locality.  ... 
doi:10.1587/transinf.2015edp7406 fatcat:xavtx5y52rfp3kajoihy7dispy

PAW: A Pattern-Aware Write Policy for a Flash Non-volatile Cache

Young-Jin KIM, Jihong KIM, Jeong-Bae LEE, Kee-Wook RIM
2010 IEICE transactions on information and systems  
In this paper, we propose a pattern-aware write cache policy, PAW for a NAND flash memory in disk-based mobile storage systems.  ...  PAW is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk.  ...  , a DRAM, and a NAND flash-based NVC at a device level.  ... 
doi:10.1587/transinf.e93.d.3017 fatcat:d4uviv2jnrb2vatcvcwolj2tdi

Energy-Aware Flash Memory Management in Virtual Memory System

Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The characteristics of flash memory are quite different from a magnetic disk. Therefore, in this paper, we revisit virtual memory system design considering limitations imposed by flash memory.  ...  The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage.  ...  Two-Level LRU (2L): Different from the TF and TFL policies, the two-level LRU policy observes a page for a period of time to determine whether this page should be allocated in HotCache.  ... 
doi:10.1109/tvlsi.2008.2000517 fatcat:bhdtgfyznnbj3n5poxn7oickdy

A Scalable and Highly Configurable Cache-Aware Hybrid Flash Translation Layer

Jalil Boukhobza, Pierre Olivier, Stéphane Rubini
2014 Computers  
This paper presents a cache-aware configurable hybrid flash translation layer (FTL), named CACH-FTL.  ...  It was designed based on the observation that most state-of-the-art flash-specific cache systems above FTLs flush groups of pages belonging to the same data block.  ...  This paper describes CACH-FTL [12] , a cache-aware configurable hybrid FTL designed to optimize write performance and embedded memory usage.  ... 
doi:10.3390/computers3010036 fatcat:hpgdwit6kfbstl5ju3vojychma

What is a good buffer cache replacement scheme for mobile flash storage?

Hyojun Kim, Moonkyung Ryu, Umakishore Ramachandran
2012 Performance Evaluation Review  
Specifically, we ask the question whether the state-of-the-art buffer cache replacement schemes proposed thus far (both flash-agnostic and flash-aware ones) are the right ones for mobile flash storage.  ...  Armed with this knowledge, we propose a new buffer cache replacement scheme called SpatialClock.  ...  FLASH-AWARE CACHE SCHEMES Ever since the appearance of NAND flash memory based solid state storage devices, multiple flash-aware buffer cache replacement schemes have been proposed.  ... 
doi:10.1145/2318857.2254786 fatcat:db5bup3btnfzfnp7tgtlg5u3bq
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