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Specification and Checking of Software Contracts for Conditional Information Flow [chapter]

Torben Amtoft, John Hatcliff, Edwin Rodríguez, Robby, Jonathan Hoag, David Greve
2010 Design and Verification of Microprocessor Systems for High-Assurance Applications  
We report on the use of this framework for a collection of SPARK examples.  ...  However, existing specification and verification environments, such as SPARK Ada, used to develop MILS applications can only capture unconditional information flows.  ...  the initial draft of the Common Criteria Protection Profile for Separation Kernels) as well as the software-based kernel in the Green Hills Integrity 178B RTOS.  ... 
doi:10.1007/978-1-4419-1539-9_12 fatcat:dqlvns7k5nhcbntvmwepwerh5q

Improved verification of hardware designs through antecedent conditioned slicing

Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
2006 International Journal on Software Tools for Technology Transfer (STTT)  
Static slicing has shown itself to be a valuable tool, facilitating the verification of hardware designs.  ...  In this paper, we present a sharpened notion, antecedent conditioned slicing that provides a more effective abstraction for reducing the size of the state space.  ...  Antecedent conditioned slicing We use conditioned slicing for verification of hardware designs described in Verilog HDL.  ... 
doi:10.1007/s10009-006-0022-x fatcat:lh633ewu5rbmzbfn5hm66mr7yq

Verifying hardware in its software context

Kurshan, Levin, Minea, Peled, Yenigun
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
We describe a method for verifying hardware whose correct behavior depends upon its software interface.  ...  Thus, independent of the interface verification problem, this gives a general method for combining partial order reduction with symbolic model-checking.  ...  Software-Centric Verification To verify software properties of a co-design, we use a software-centric approach.  ... 
doi:10.1109/iccad.1997.643621 fatcat:uqoz5k7vlfflzpepn73fbwuaku

Haifa verification conference 2007

Karen Yorav
2009 International Journal on Software Tools for Technology Transfer (STTT)  
HVC's goal is to serve as a venue for researchers from all fields of verification, enabling them to exchange ideas and learn from one another.  ...  The scope of this conference covers all types of verification of both hardware and software systems.  ...  Other examples were taken from a paper by Shmuel Ur and Avi Ziv [6] , where they discuss the similarities between software testing and hardware simulation, and the need for cross-fertilization between  ... 
doi:10.1007/s10009-009-0116-3 fatcat:7vk47ug26nfvvmmffu5c7inycu

Code Formal Verification of Operation System

Yu Zhang, Yunwei Dong, Huo Hong, Fan Zhang
2010 International Journal of Computer Network and Information Security  
Formal verification is the only known way to guarantee that a system is free of programming errors.  ...  We present a case study to the verification of real-world C systems code derived from an implementation of μC/OS -II in the end.  ...  software design, evaluation method cannot solve embedded software reliability and safety design problems in depth.  ... 
doi:10.5815/ijcnis.2010.02.02 fatcat:2xx46lr5grh4tb4hpulujdxh3q

Software Reliability through Theorem Proving
English

S. Murthy, K. Sekharam
2009 Defence Science Journal  
Early detection of errors in software requirements, designs and implementation, need rigorous verification and validation techniques.  ...  Theorem proving is a powerful formal verification technique that enhances the software reliability for missioncritical aerospace applications.  ...  To verify the unreachability for the statements given in the if and else statements, post condition property has to be designed accordingly.  ... 
doi:10.14429/dsj.59.1527 fatcat:vneggdcluzf6botcb2mv3ve4ju

Analytic verification of flight software

M. Lowry, D. Dvorak
1998 IEEE Intelligent Systems and their Applications  
Acknowledgments The research described in this aaicle was carried out by members of the Automated Software Engineering group at NASA Ames Research Center, and by the Jet Propulsion Laboratory, Califomia  ...  This will let developers use model checking directly as part of a debugging package for autonomy-software design.  ...  Anticipating all these interleavings can be difficult for a human designer; model checking can find subtle, pernicious interactions that violate correctness conditions.  ... 
doi:10.1109/5254.722359 fatcat:nplizd5vffahzhohpep7yc76va

The Study on Formal Verification of OS Kernel

Yu Zhang, Yunwei Dong, Zhongqiu Zhang, Hong Huo, Fan Zhang
2011 International Journal of Wireless and Microwave Technologies  
Formal verification is the only known way to guarantee that a system is free of programming errors.  ...  We present a case study to the verification of real-world C systems code derived from an implementation of μC/OS -II in the end.  ...  software design, evaluation method cannot solve embedded software reliability and safety design problems in depth.  ... 
doi:10.5815/ijwmt.2011.03.10 fatcat:g3wghju2ofhvjnvdjucpq72o6q

SW-VHDL Co-Verification Environment Using Open Source Tools

Maria Muñoz-Quijada, Luis Sanz, Hipolito Guzman-Miranda
2020 Electronics  
The verification of complex digital designs often involves the use of expensive simulators.  ...  external processor, such as a user/operator software running on an external PC.  ...  The authors would like to also thank the GNU project for their work on GCC and GNU make, and the Python Software Foundation for their work on Python.  ... 
doi:10.3390/electronics9122104 fatcat:kuirfwlgyfgtxbsaimwfplw6ta

FPGA-based verification methodology of SoC-type CMOS image signal processor

YounSun Kim, Hong-Sik Kim, Raymond Lee, Sungho Kang
2009 2009 IEEE International SOC Conference (SOCC)  
This paper describes a FPGA-based verification methodology for the image signal processor (ISP) of system-on-chip (SoC) type CMOS image sensor.  ...  As a verification method, 4-step verification strategy comprised of ARMcore based platform verification, system verification, algorithm verification and performance verification is used.  ...  For this, host interface handling software, command decoding software and output formatting control software are integrated into the system control software.  ... 
doi:10.1109/soccon.2009.5398051 dblp:conf/socc/KimKLK09 fatcat:25upyihruzgsxpn3fmedslhq5m

Refinement of Safety-Related Hazards into Verifiable Code Assertions [chapter]

Ken Wong, Jeff Joyce
1998 Lecture Notes in Computer Science  
The development of the safety code assertions increases the feasibility of using code verification tools such as SPARK Examiner in the safety verification of large software-intensive systems.  ...  This paper presents a process for the stepwise refinement of safety code assertions from identified system hazards. The code assertions are intended for use in system safety verification.  ...  There are other problems with using code verification tools for the safety verification of a large software system.  ... 
doi:10.1007/3-540-49646-7_27 fatcat:hoysbxx72fbvrb6o5zxrad6a3y

Towards Customizable CPS: Composability, Efficiency and Predictability [chapter]

Wang Yi
2017 Lecture Notes in Computer Science  
This is due to the lack of techniques to preserve crucial safety conditions for the modified system, which severely restricts the benefits of software.  ...  The tools shall support not only verification, but also code generation tailored for both co-simulation (interfaced) with existing design tools such as Open Modelica (for modeling and simulation of physical  ...  tailored for operation-time verification of the two conditions are available.  ... 
doi:10.1007/978-3-319-68690-5_1 fatcat:wwfoniwr2zayfcvigxggfaed2a

Formal Verification of Contractual Software Architectures using SPIN

Mert Ozkaya
2015 Malaysian Journal of Computer Science  
In this paper, I discuss XCD and its support for formal verification of software architectures through a simple shared-data access case study.  ...  Software architectures let designers specify systems in terms of components and their relations (i.e., connectors).  ...  So, designers can use the verification commands given in Listing 6 for detecting race conditions too.  ... 
doi:10.22452/mjcs.vol28no4.4 fatcat:wakc5wjuwbbhbb6ptg46t26mkq

Poster Abstract: Getting Out of the Way -- Safety Verification without Compromise

Theodore P. Pavlic, Sai Prathyusha Peddi, Paolo A.G. Sivilotti, Bruce W. Weide
2012 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems  
The intelligent transportation systems problems of adaptive cruise control and variable timing for traffic intersection signals are explored with emphasis on verification of safety properties.  ...  Moreover, designs for ACC for convoying put emphasis on properties like string stability [1] and take safety for granted.  ...  From Model Checking to Software Verification To verify the safety of software (as opposed to behavioral models) in hybrid systems, we embed the continuous dynamics into the software specifications themselves  ... 
doi:10.1109/iccps.2012.51 dblp:conf/iccps/PavlicPSW12 fatcat:rqgtwqhrofc6xpg3zihmyr7snu

SDLcheck: A Model Checking Tool [chapter]

Vladimir Levin, Hüsnü Yenigün
2001 Lecture Notes in Computer Science  
SDLcheck is also capable of supporting software/hardware co-design verification.  ...  For software verification, combining IF [5] and SPIN [6], as reported in [7], supports complementary sets of model checking optimizations.  ...  SDLcheck is also capable of supporting software/hardware co-design verification.  ... 
doi:10.1007/3-540-44585-4_36 fatcat:3cros567yjfmti5tm2zi3h4hte
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