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Power comparison of an asynchronous and synchronous network on chip router

Pooria M. Yaghini, Ashkan Eghbal, S. A. Asghari, H. Pedram
2009 2009 14th International CSI Computer Conference  
However, the power consumption of routing unit component in asynchronous design is lower than synchronous one.  ...  Their designs are similar except the extra links which are in charge of handshaking processes in asynchronous architecture.  ...  The router is simulated with CSP-Verilog (communicating sequential processes) language as an asynchronous one.  ... 
doi:10.1109/csicc.2009.5349422 fatcat:yq5c4xbognbzndvv3vge6cuqsm

An Efficient Prototype for Gals Systems in Asynchronous Network-on-Chips through Multiclocking

2017 International Journal of Science and Research (IJSR)  
Modularity property of asynchronous circuits is fully oppressed to design regular distributed link topologies by the means of basic topology-free building blocks, with a focus and special design effort  ...  N etworkon-chips vigorously benefit to such a globally asynchronous design methodology.  ...  Since the components are not active most of time, the asynchronous design will be useful for reduction in power. This paper deals with network on chip based on asynchronous approach.  ... 
doi:10.21275/art20175428 fatcat:f7ipsqy4evgeha7olfd4p3ex6u

Model-based Design of Reusable Secure Connectors

Michael Eonsuk Shin, Hassan Gomaa, Don Pathirage
2017 ACM/IEEE International Conference on Model Driven Engineering Languages and Systems  
Each secure connector is designed as a composite component that encapsulates both security pattern and communication pattern components.  ...  The secure connectors are designed separately from application components by reusing the appropriate communication pattern between components as well as the security patterns required by these components  ...  message communication with reply, synchronous message communication without reply, asynchronous message communication, and bidirectional asynchronous message communication [5] .  ... 
dblp:conf/models/ShinGP17 fatcat:facq6bxmdfbzll767cm5br4wea

Performance Engineering of Component-Based Distributed Software Systems [chapter]

Hassan Gomaa, Daniel A. Menascé
2001 Lecture Notes in Computer Science  
This paper investigates the design and performance modeling of component interconnection patterns, which define and encapsulate the way client and server components communicate with each other.  ...  We start with UML design models of the component interconnection patterns. These designs are performance annotated using an XML-type notation.  ...  client and server components communicate with each other.  ... 
doi:10.1007/3-540-45156-0_3 fatcat:nswuj3twb5g2xj4wsyzf7qghka

Online Creative Learning Model: Effective Asynchronous Integration

2019 Journal of Organizational Psychology  
With the current course content delivery modality reliability issues plaguing many universities, it is imperative that we, as educators, understand our critical roles.  ...  A fundamental argument in asynchronous learning is the dichotomy between constructivism and objectivism and overall student experience.  ...  Leading communication -includes both upward and downward communication with instructors 2.  ... 
doi:10.33423/jop.v19i2.2048 fatcat:pwjf6ivgjjhvphaa2bicgkvm7i

Scalable formal design methods for asynchronous VLSI

Rajit Manohar
2002 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '02  
This lecture will provide an overview of the field of asynchronous VLSI, and show how formal methods have played a critical role in the design of complex asynchronous systems.  ...  In particular, I will talk about program transformations and their application to asynchronous VLSI, as well as describe a simple language that I developed to describe these circuits and aid in their validation  ...  In asynchronous (clockless) systems, synchronization is implemented by using message-passing primitives or local barriers between concurrent components that communicate with each other.  ... 
doi:10.1145/503272.503295 dblp:conf/popl/Manohar02 fatcat:qckwiwkwnjej7kj2dk6oyxfrzi

Asynchronous Design—Part 1: Overview and Recent Advances

Steven M. Nowick, Montek Singh
2015 IEEE design & test  
Foundations Asynchronous systems are typically organized as a set of components which communicate and synchronize using handshaking channels.  ...  systems is a hybrid approach, integrating synchronous components (i.e. cores, memories, accelerators, I/O units, etc.) using an asynchronous communication network, which together form a globally-asynchronous  ...  His research interests include asynchronous and mixed-timing circuits and systems; CAD tools for design, analysis, and optimization; high-speed and low-power VLSI design; and applications to emerging computing  ... 
doi:10.1109/mdat.2015.2413759 fatcat:g5qkrrrdujdkld6fsx3fhyrem4

Compiling the language Balsa to delay insensitive hardware [chapter]

Andrew Bardsley, Doug Edwards
1997 Hardware Description Languages and their Applications  
The handshake circuits are subsequently mapped to CMOS implementations of 4-phase bundled-data asynchronous circuits by a suite of parameterised component-generating scripts within the Cadence design framework  ...  Balsa is derived from CSP with similar language constructs and a single-bit granularity type system.  ...  In spite of the now proven feasibility of asynchronous techniques, their widespread acceptance by the wider design community is likely impeded by the lack of automated synthesis or peculiarly asynchronous  ... 
doi:10.1007/978-0-387-35064-6_11 fatcat:ouiwgcxlhbfbjf6gmgarjvckza

Asynchronous on-chip networks

M. Amde, T. Felicijan, A. Efthymiou, D. Edwards, L. Lavagno
2005 IEE Proceedings - Computers and digital Techniques  
The authors survey various methodologies used for leveraging asynchronous on-chip communication.  ...  A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms.  ...  This leads to a design flow fairly similar to the synchronous flow but with a few additional components which enable asynchronous communication.  ... 
doi:10.1049/ip-cdt:20045093 fatcat:jedytsssjfcmjoyrajrn47ue6e

Mapping UML Component Specifications to JEE Implementations

Jyhjong Lin
2007 Journal of Computer Science  
With such a practical mapping, software systems can be developed in a more effective way by specifying requirements in UML Components and implementing software components in EJB with the communicating  ...  to a component model that particularly takes into consideration of the communicating of synchronous/asynchronous messages.  ...  MAPPING APPROACHES For the design mapping in CbSE from a component specification to a component model with emphasis on the communicating of synchronous/asynchronous messages, the component specification  ... 
doi:10.3844/jcssp.2007.780.785 fatcat:wwws3liztraa3i6confzimiksy

Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware

X. Wang, M. Kwiatkowska, G. Theodoropoulos, Q. Zhang
2005 Electronical Notes in Theoretical Computer Science  
We demonstrate the feasibility of our approach by automatically detecting errors due to delay sensitivity and deadlock in simple asynchronous hardware components.  ...  Formal verification is increasingly important in asynchronous circuit design, since the lack of a global synchronizing clock makes errors due to concurrency (e.g., deadlocks) virtually impossible to detect  ...  A channel is two-way and associated with delay. Components communicate by sending/receiving signals with non-blocking semantics.  ... 
doi:10.1016/j.entcs.2005.04.014 fatcat:crqwkfv6izgablu5gfyzkicwse

Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages

Jian Liu, Steven M. Nowick, Mingoo Seok
2013 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems  
flexible and distributed assembly and communication of components.  ...  Instead, they are distributed hardware systems where multiple components coordinate and synchronize at their own rate on communication channels.  ...  ROBUST ENCODING FOR GLOBAL ASYNCHRONOUS COMMUNICATION This aim of this research is to develop practical codes, and hardware support, for robust asynchronous communication.  ... 
doi:10.1109/async.2013.29 dblp:conf/async/LiuNS13 fatcat:pgi4on5mbffj3fylrygmhghspy

Asynchronous Design—Part 2: Systems and Methodologies

Steven M. Nowick, Montek Singh
2015 IEEE design & test  
h THIS TWO-PART article aims to provide both a short historical and technical overview of asynchronous design, as well as a snapshot of the state of the art.  ...  Part 1 covered foundations of asynchronous design, and highlighted recent applications, including commercial advances and use in emerging application areas.  ...  On occasion, designers have tried to harness asynchronous benefits by targeting an individual component for asynchronous implementation within a complex clocked system.  ... 
doi:10.1109/mdat.2015.2413757 fatcat:bpxnljdkofh6ppyovk6sp4pknm

A Novel Fifo Design For Data Transfer In Mixed Timing Systems

Mansi Jhamb, R. K. Sharma, A. K. Gupta
2014 Zenodo  
In order to solve this problem, a novel modified asynchronous FIFO design is proposed. The results obtained from proposed design are in perfect accordance with theoretical expectations.  ...  The proposed asynchronous FIFO design outperforms the existing design in terms of accuracy and speed.  ...  Asynchronous FIFO is an important component for the efficient data transfer in asynchronous communication [3] .  ... 
doi:10.5281/zenodo.1092181 fatcat:4bdbmskvcjg2lpdt6efroe725u

Click-Based Asynchronous Mesh Network with Bounded Bundled Data

Anping He, Guangbo Feng, Jilin Zhang, Pengfei Li, Yong Hei, Hong Chen
2018 Proceedings of the 47th International Conference on Parallel Processing - ICPP 2018  
Compared to designs that use other asynchronous circuit families with Celements and four-phase bundled data, our two-phase Click-based Bounded Bundled Data design is faster, but introduces phase skews  ...  We believe that with the non-delay-branch designs, our asynchronous mesh network could offer 10.1M routes per second for a 1 × 1 network and 5.33M routes per second for 2 × 2 or 5.06M for 4 × 4 networks  ...  The click controller in this paper is directly from ARC, and the asynchronous mesh design, as well as this paper, would never succeed without their help.  ... 
doi:10.1145/3225058.3225118 dblp:conf/icpp/HeFZLHC18 fatcat:eyrfolumhra4njyngrbzhl3w7u
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