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Design space exploration for partially reconfigurable architectures in real-time systems

François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini
2013 Journal of systems architecture  
In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints,  ...  enabling Design Space Exploration (DSE) at the early stages of the development.  ...  dynamic and partial reconfiguration.  ... 
doi:10.1016/j.sysarc.2013.06.007 fatcat:dixe4ecqyrce7prltrqkvrxaze

Perfecto

Pao-Ann Hsiung, Chao-Sheng Lin, Chih-Feng Liao
2008 ACM Transactions on Reconfigurable Technology and Systems  
To cope with increasing demands for higher computational power and greater system flexibility, dynamically and partially reconfigurable logic has started to play an important role in embedded systems and  ...  In this work, we present a system-level framework, called Perfecto, which is able to perform rapid exploration of different reconfigurable design alternatives and to detect system performance bottlenecks  ...  Perfecto can be used not only to explore the design space of dynamically and partially reconfigurable systems, but also to explore the construction of the design algorithms that must be implemented into  ... 
doi:10.1145/1391732.1391737 fatcat:3suggtppv5celpv54gjq2rveoi

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

Dirk Stroobandt, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, Xinyu Niu, Dionisios Pnevmatikatos, Amit Kulkarni, Elias Vansteenkiste, Wayne Luk (+7 others)
2016 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)  
In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental  ...  EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low  ...  In this context, EXTRA will explore (partial) reconfigurability as a specific design feature in future HPC systems, aiming to enable it fully in new reconfigurable architectures, new design tools, and  ... 
doi:10.1109/recosoc.2016.7533896 dblp:conf/recosoc/StroobandtVCKBC16 fatcat:3hjjgwqrdzf5notzalewyjdybm

Symbolic design space exploration for multi-mode reconfigurable systems

Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
2011 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11  
In addition, we introduce an architectural model that allows to express the characteristics of nowadays partially reconfigurable architectures, focusing on FPGAs.  ...  We develop a symbolic encoding of this novel system specification, which allows to perform a unified system synthesis for allocation, binding, placement of partially reconfigurable modules, and routing  ...  CONCLUSION In this work, we propose a design space exploration for multi-mode reconfigurable embedded systems.  ... 
doi:10.1145/2039370.2039393 dblp:conf/codes/WildermannRZT11 fatcat:w2b6iwn57bhdbovygz7x5z54bu

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

Y.E. Krasteva, E. de la Torre, T. Riesgo
2008 2008 34th Annual Conference of IEEE Industrial Electronics  
The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs.  ...  Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration.  ...  ACKNOWLEDGMENT The authors wish to express their gratitude to the Departamento de Fundamentos da Computacao, Pontificia Universidade Catolica do Rio Grande do Sul, specially to Ney Calazans, for providing  ... 
doi:10.1109/iecon.2008.4758347 fatcat:pljvonyew5ed7fd7pqvuxugfbu

Exploration, Partitioning and Simulation of Reconfigurable Systems (Exploration, Partitionierung und Simulation rekonfigurierbarer Systeme)

Florian Dittmann, Franz J. Rammig, Martin Streubühr, Christian Haubelt, Andreas Schallenberg, Wolfgang Nebel
2007 it - Information Technology  
Reconfigurable devices in large complex systems allow the reduction of the amount of required resources. They serve as run-time re-usable devices for performance critical data-oriented processes.  ...  design space exploration.  ...  Conclusion In this paper we presented a concept for a tool-assisted design space exploration approach for systems containing dynamically hardware reconfigurable resources.  ... 
doi:10.1524/itit.2007.49.3.149 fatcat:gaabsiltkzhq3h54wcou2qw6he

Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems

Florian Dittmann, Marcelo Gotz, Achim Rettberg
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
In this paper, we introduce a synthesis methodology for reconfigurable systems that respects the specific requirements of run-time reconfiguration.  ...  When reconfigurable devices are used in modern embedded systems and their capability to adapt to changing application requirements becomes an issue, comprehensive modeling and design methods are required  ...  In this contribution, we shape and improve approaches and methods of embedded system design for the design of partially and run-time reconfigurable fabrics that themselves can be part of a complex systems  ... 
doi:10.1109/ipdps.2007.370388 dblp:conf/ipps/DittmannGR07 fatcat:pzitl37wtfearcymr4bo5l2nie

Design Space Exploration of Configuration Manager for Network Processing Applications

Christoforos Kachris, Stamatis Vassiliadis
2007 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation  
In this paper, a design space exploration framework is presented to design a reconfigurable platform for multi-service network processing applications.  ...  Furthermore, the design of an efficient configuration manager is presented in which the platform adaptation is performed for optimum speedup with minimum overhead taking into account the reconfiguration  ...  All of these frameworks are used to perform design space exploration to find the optimum static architecture for specific network traffic.  ... 
doi:10.1109/icsamos.2007.4285731 dblp:conf/samos/KachrisV07 fatcat:n6im4bqc6rf7baifzpl7lpckyu

A Fast Emulation-Based NoC Prototyping Framework

Yana E. Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo
2008 2008 International Conference on Reconfigurable Computing and FPGAs  
The paper describes all the building elements of the proposed solution: the used partial reconfiguration approach, the design space exploration framework itself, and the data measuring system.  ...  For this aim, partial reconfiguration capabilities of some state of the art FPGAs have been developed and applied.  ...  ACKNOWLEDGMENT The authors wish to express their gratitude to the Departamento de Fundamentos da Computacao, Pontificia Universidade Catolica do Rio Grande do Sul, specially to Ney Calazans, for providing  ... 
doi:10.1109/reconfig.2008.74 dblp:conf/reconfig/KrastevaCTR08 fatcat:jm4uwu4qk5h4xbl5infdsk5fpe

PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures

Riccardo Cattaneo, Riccardo Bellini, Gianluca Durelli, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto
2014 2014 IEEE International Parallel & Distributed Processing Symposium Workshops  
In this work, we propose PaRA-Sched, an improvement for a state of the art, highly automated design methodology that allows the designer to rapidly explore the impact of PDR employment during the early  ...  Partial and Dynamic Reconfiguration (PDR), in this context, is a specific feature whose potential is undiscussed but yet to uncover.  ...  Acknowledgments This work was partially funded by the European Commission in the context of the FP7 FASTER project (#287804).  ... 
doi:10.1109/ipdpsw.2014.32 dblp:conf/ipps/CattaneoBDPSS14 fatcat:uwn4oooj3falnix2dz7k5qu2ce

Selected Papers from ReConFig 2008

Lionel Torres, Cesar Torres
2009 International Journal of Reconfigurable Computing  
The development, exploration, and validation methodology of real-time operating systems for reconfigurable Systems-on-Chip is covered in "OveRSoC: a framework for the exploration of RTOS for RSoC platforms  ...  Zambrano et al. in "Parallel processor for 3D recovery from optical flow" present a parallel processor for 3D recovery from optical flow under real-time constraints. The  ...  The development, exploration, and validation methodology of real-time operating systems for reconfigurable Systems-on-Chip is covered in "OveRSoC: a framework for the exploration of RTOS for RSoC platforms  ... 
doi:10.1155/2009/869329 fatcat:zqfusxerbfehlaaycfy47dofly

A Roadmap for Autonomous Fault-Tolerant Systems

X. Iturbe, K. Benkrid, T. Arslan, I. Martinez, M. Azkarate, M. D. Santambrogio
2010 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP)  
Finally, the general structure and organization of a Reliable Reconfigurable Real-Time Operating System (R3TOS) is presented.  ...  An Autonomous Fault-Tolerant System (AFTS) refers to a system that is able to configure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate  ...  in real-time.  ... 
doi:10.1109/dasip.2010.5706281 dblp:conf/dasip/IturbeBAMAS10 fatcat:nzil4y2drfhdfgcqlslf6ij6jy

Self-Adaptive Architecture for Multi-Sensor Embedded Vision System [chapter]

Ali Isavudeen, Eva Dokladalova, Nicolas Ngan, Mohamed Akil
2016 Lecture Notes in Computer Science  
In this implementation, adaptation of the architecture consists in Dynamic and Partial Reconfiguration of FPGA.  ...  Reconfigurable architecture makes possible flexible computing while respecting the latter constraints. Many reconfigurable architectures for vision application have been proposed in the past.  ...  A partial reconfiguration time of 75 ms is to long compared to usual times in Xilinx FPGA-based designs. This time represents about two image frames time in a 25 fps system.  ... 
doi:10.1007/978-3-319-29817-7_7 fatcat:siy5qu6ayvdibiehm55p4upgcu

Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

Chun-Hsian Huang, Pao-Ann Hsiung, Jih-Sheng Shen
2010 Journal of systems architecture  
To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and  ...  Furthermore, a UMLbased hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture.  ...  hardware tasks in real-time online system environments.  ... 
doi:10.1016/j.sysarc.2010.07.007 fatcat:6lq7ebanfzd4vdhgprsy7p4uxe

Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems

Weixun Wang, Prabhat Mishra
2009 2009 IEEE Computer Society Annual Symposium on VLSI  
While cache reconfiguration is successful in desktop-based systems, it is not directly applicable in real-time systems due to timing constraints.  ...  This paper efficiently integrates cache reconfiguration in soft real-time systems with a unified two-level cache hierarchy.  ...  Our previous work [15] have explored the use of one-level reconfigurable cache in soft real-time systems.  ... 
doi:10.1109/isvlsi.2009.22 dblp:conf/isvlsi/WangM09 fatcat:etkmuy7kwvddpahxatub2b4cwq
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