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Automatic generation of maps of memory accesses for energy-aware memory management

Florin Balasa, Ilie I. Luican, Hongwei Zhu, Doru V. Nasui
2009 2009 IEEE International Conference on Acoustics, Speech and Signal Processing  
the system development process on the exploration of the memory subsystem in order to achieve a cost-optimized design.  ...  Tested on a twolayer memory hierarchy (scratch-pad and off-chip memories), this algorithm led to significant savings of energy in comparison to previous computation models.  ...  the system development process on the exploration of the memory subsystem in order to achieve a cost-optimized design.  ... 
doi:10.1109/icassp.2009.4959662 dblp:conf/icassp/BalasaLZN09 fatcat:pkvoigvhyndthg4zrntofazgwq

Scratchpad memory

Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel
2002 Proceedings of the tenth international symposium on Hardware/software codesign - CODES '02  
A B S T R A C T In this paper we address the problem of on-chip memory selection for computationally intensive applications, by proposing scratch pad memory as an alternative to cache.  ...  Area and energy for different scratch pad and cache sizes are computed using the CACTI tool while performance was evaluated using the trace results of the simulator.  ...  This algorithm identifies the frequently referred data and instruction blocks and maps to the scratch pad memory address space.  ... 
doi:10.1145/774789.774805 dblp:conf/codes/BanakarSLBM02 fatcat:jwni4noqyjaohou4balukpploa

A Novel Data-Parallel Coprocessor for Multimedia Signal Processing

Lai Mingche, Dai Kui, Lu Hong-yi, Wang Zhi-ying
2006 2006 IEEE International Conference on Multimedia and Expo  
The coprocessor consists of two powerful arithmetic clusters, the stream memory as well as the optimized data transport network, and is good at exploiting the data parallelism in the computation intensive  ...  multimedia applications.  ...  ACKNOWLEDGMENT The authors would like to thank Andrea Cilio and his colleagues in Delft technology university of Netherlands for their great help.  ... 
doi:10.1109/icme.2006.262513 dblp:conf/icmcs/MingcheKHZ06 fatcat:5nzwg2ti6zhwzc36agvnasdrem

Software controlled memory layout reorganization for irregular array access patterns

Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek
2007 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07  
Many embedded array-intensive applications have irregular access patterns that are not amenable to static analysis for extraction of access patterns, and thus prevent efficient use of a Scratch Pad Memory  ...  of the generated application code to steer mapping of data to the SPM to yield performance and energy benefits.  ...  against a traditional cache based memory subsystem for their ability to exploit data reusability of the data accesses in a number of multimedia, communication, and encryption applications.  ... 
doi:10.1145/1289881.1289915 dblp:conf/cases/ChoIDYP07 fatcat:tdjxci5r4nalxlm3hvk3sp6veu

DRDU

Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt
2007 ACM Transactions on Design Automation of Electronic Systems  
In multimedia and other streaming applications, a significant portion of energy is spent on data transfers.  ...  In this article we present an automated approach for analyzing these opportunities in a program that allows modification of the program to use custom scratch-pad memory configurations comprising a hierarchical  ...  The problem of design space exploration (selecting which of the buffers should be used and mapping them to the scratch-pad memory hierarchy) is not in the scope of this article and has been addressed previously  ... 
doi:10.1145/1230800.1230807 fatcat:5vdyhfx7rbdq3mk7zjkbcygwei

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications

Doosan Cho, S. Pasricha, I. Issenin, N.D. Dutt, Minwook Ahn, Yunheung Paek
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Guided by compiler analysis for generating scratch pad data layouts and hardware components for tracking dynamic memory accesses, the scratch pad data layout adapts to an input data pattern with the help  ...  of a runtime scratch pad memory manager incorporated in the OS.  ...  Guided by compiler analysis for generating scratch pad data layouts and hardware components for tracking dynamic memory accesses, the scratch pad data layout adapts to an input data pattern with the help  ... 
doi:10.1109/tcad.2009.2014002 fatcat:dhlcctxwxjavdehpujptcgacdm

Memory Architecture Exploration Framework for Cache Based Embedded SOC

T.S. Rajesh Kumar, C.P. Ravikumar, R. Govindarajan
2008 21st International Conference on VLSI Design (VLSID 2008)  
We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few  ...  Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications.  ...  Our framework integrates memory exploration, data partitioning between SPRAM and Cache, and cache-conscious data layout to explore memory design space and presents a list of Pareto Optimal solutions.  ... 
doi:10.1109/vlsi.2008.113 dblp:conf/vlsid/KumarRG08 fatcat:pnp5hbtfq5gw5iu6btqmttrgaq

On combining iteration space tiling with data space tiling for scratch-pad memory systems

Chunhui Zhang, Fadi Kurdahi
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
However, more and more real-time embedded systems are adopting Scratch-Pad Memories (SPMs) which emphasize on the management of data flow through data-oriented tiling.  ...  An important real-life application, matrix multiply, is selected to illustrate how we combine the mismatched iteration space tiling with data space tiling for optimal solutions.  ...  CONCLUSION This paper made a preliminary step towards combining iteration space tiling with data space tiling for scratch-pad memory systems.  ... 
doi:10.1145/1120725.1120770 dblp:conf/aspdac/ZhangK05 fatcat:dpbdbdz7xzcrzd5qrsqbkowspa

Leakage-aware scratch-pad memory banking for embedded multidimensional signal processing

Florin Balasa, Noha Abuaesh, Cristian V. Gingu, Doru V. Nasui
2014 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
This paper addresses the problem of energy-aware on-chip memory banking, taking into account -during the exploration of the search space -the idleness time intervals of the data mapped into the memory  ...  The proposed approach proved to be computationally fast and very efficient when tested for several data-intensive applications, whose behavioral specifications contain multidimensional arrays as main data  ...  phase the data assignment to the memory layers and the mapping of signals to the physical memories.  ... 
doi:10.1109/icassp.2014.6854559 dblp:conf/icassp/BalasaAGN14 fatcat:ne7zb5n7tbczhnqegtrutaxpby

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

T.S. Kumar, C.P. Ravikumar, R. Govindarajan
2007 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)  
We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours  ...  This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design  ...  In our method the data layout is not fixed and hence it explores the complete design space with respect to performance and power. Performance-energy design space exploration is presented in [5] .  ... 
doi:10.1109/vlsid.2007.102 dblp:conf/vlsid/KumarRG07 fatcat:m5vpkwv2ibfa3azvl4x4seflny

APEX

Peter Grun, Nikil Dutt, Alex Nicolau
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
Although real-life applications contain a large number of memory references to a diverse set of data structures, a significant percentage of all memory accesses in the application are generated from a  ...  We use a heuristic to prune the design space, guiding the exploration towards the best cost/gain ratios.  ...  ACKNOWLEDGMENTS We would like to acknowledge and thank Ashok Halambi, Prabhat Mishra, Srikanth Srinivasan, Partha Biswas, Aviral Shrivastava, Radu Cornea and Nick Savoiu for their contributions to the  ... 
doi:10.1145/500001.500007 fatcat:46jwo5b3rjdxfgppexowfljsna

APEX

Peter Grun, Nikil Dutt, Alex Nicolau
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
Although real-life applications contain a large number of memory references to a diverse set of data structures, a significant percentage of all memory accesses in the application are generated from a  ...  We use a heuristic to prune the design space, guiding the exploration towards the best cost/gain ratios.  ...  ACKNOWLEDGMENTS We would like to acknowledge and thank Ashok Halambi, Prabhat Mishra, Srikanth Srinivasan, Partha Biswas, Aviral Shrivastava, Radu Cornea and Nick Savoiu for their contributions to the  ... 
doi:10.1145/500002.500007 fatcat:uul3frztzve3zm56fdzy5q7hoe

Using FORAY Models to Enable MPSoC Memory Optimizations

Ilya Issenin, Nikil Dutt
2007 International journal of parallel programming  
We demonstrate how FORAY-GEN enhances applicability of other memory subsystem optimization approaches, resulting in an average of two times increase in the number of memory references that can be analyzed  ...  In this paper, we introduce the FORAY model of a program that allows aggressive analysis of the application's memory behavior and enables such optimizations on arbitrary code which are not possible to  ...  ACKNOWLEDGMENTS This work was partially supported by NSF grants CCR-0203813 and CCR-0205712. This is an expanded version of our DATE 2005 paper (9)  ... 
doi:10.1007/s10766-007-0041-6 fatcat:2soi44d3tnaafb2zc67s24b7yy

Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic

M.D. Galanis, G. Dimitroulakos, C.E. Goutis
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Large values of Instructions Per Cycle were achieved on two Reconfigurable Arrays that resulted in high-performance kernel mapping.  ...  Analytical results derived from mapping five real-life DSP applications on eight different instances of a generic system architecture are presented.  ...  The scratch-pad serves as a local memory for quickly loading data in the PEs of the CGRA.  ... 
doi:10.1109/ipdps.2006.1639348 dblp:conf/ipps/GalanisDG06 fatcat:eveltrvh3bdt3mrowu2glmulf4

Some Results on Mean Square Error for Factor Score Prediction

Wim P. Krijnen
2006 Psychometrika  
We demonstrate how FORAY-GEN enhances applicability of other memory subsystem optimization approaches, resulting in an average of two times increase in the number of memory references that can be analyzed  ...  In this paper, we introduce the FORAY model of a program that allows aggressive analysis of the application's memory behavior and enables such optimizations on arbitrary code which are not possible to  ...  ACKNOWLEDGMENTS This work was partially supported by NSF grants CCR-0203813 and CCR-0205712. This is an expanded version of our DATE 2005 paper (9)  ... 
doi:10.1007/s fatcat:z2np3zq5abamlbwce3u6u77u5a
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