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Design productivity of a high level synthesis compiler versus HDL

Maxime Pelcat, Cedric Bourrasset, Luca Maggiani, Francois Berry
2016 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)  
In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware description.  ...  To demonstrate the Design Productivity evaluation method, an HLS compiler based on the CAPH language is compared to manual VHDL writing. The causes that make VHDL lower level than CAPH are discussed.  ...  However, High-Level Synthesis (HLS) methods are currently becoming market practice in the industry [2] . They raise the level of abstraction of the code manipulated by designers higher than RTL.  ... 
doi:10.1109/samos.2016.7818341 dblp:conf/samos/PelcatBMB16 fatcat:w2zkoy7gyzdo3ncdnnkeecsitu

Automatic performance model synthesis from hardware verification models

Robert H. Bell, Matyas Sustik, David W. Cummings, Jonathan R. Jackson
2011 Proceeding of the second joint WOSP/SIPEW international conference on Performance engineering - ICPE '11  
We present a case-study that shows that even the simplest proposed transformations on a high-performance IBM L2 cache design result in a simulation speedup of 3.9, with evidence that an order of magnitude  ...  In either case, many man-months of work may be required to write the new model and validate design details against a prior or current design.  ...  Figure 7 depicts a reduced HDL model with one RLM abstracted from low-level HDL to high-level C-code, with a final transformation of the C-code to new design functionality for a design study.  ... 
doi:10.1145/1958746.1958816 dblp:conf/wosp/BellSCJ11 fatcat:fyztn3fomjbfdf2sdg7xajvgyq

FPGAs, Programming Models, and Kit Cars

Vaughn Betz
2011 IEEE Design & Test of Computers  
First, recent results in high-level synthesis (HLS) show that we can design many custom data paths in variants of C and achieve good performance while greatly improving productivity.  ...  This eliminates the tedious task of writing low-level hardware and software to interface an FPGA into a CPU systemÀ À the compiler will now generate it automatically.  ...  First, recent results in high-level synthesis (HLS) show that we can design many custom data paths in variants of C and achieve good performance while greatly improving productivity.  ... 
doi:10.1109/mdt.2011.83 fatcat:dkwpka7svnekxomyt5xdu65zoe

High-Level Synthesis: Past, Present, and Future

G. Martin, G. Smith
2009 IEEE Design & Test of Computers  
All the user experiences discussed High-Level Synthesis Figure A . A Sales of electronic system-level synthesis tools. (Source: Gary Smith EDA statistics.)  ...  both synthesis and high-level synthesis at a time when the only commercial EDA industry products were the physical layout machines offered by companies such as Calma, Applicon, and Computervision.  ... 
doi:10.1109/mdt.2009.83 fatcat:yimb2nmhrzgbhnaw2nluqewnea

An industrial view of electronic design automation

D. MacMillen, R. Camposano, D. Hill, T.W. Williams
2000 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation.  ...  In particular, we will focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test.  ...  First, by describing a system at a higher level of abstraction, there is a boost in design productivity.  ... 
doi:10.1109/43.898825 fatcat:hhk7zrepyfcyxgizvotqck7cei

Comparing Signal Processing Hardware-Synthesis Methods Based on the Matlab Tool-Chain

Rico Zoss, Andreas Habegger, Vinzenz Bandi, Josef Goette, Marcel Jacomet
2011 2011 Sixth IEEE International Symposium on Electronic Design, Test and Application  
Various commercial and academic tools are available for the synthesis of hardware algorithms.  ...  We use several designs as case studies to investigate the effect of the tool features with respect to hardware architecture and design flexibility.  ...  High-level synthesis has been a research topic for many years.  ... 
doi:10.1109/delta.2011.58 dblp:conf/delta/ZossHBGJ11 fatcat:kc5w2zd4yfd3tb4zv3z4bvk22m

High level synthesis: Where are we? A case study on matrix multiplication

Sam Skalicky, Christopher Wood, Marcin Lukowiak, Matthew Ryan
2013 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)  
Such implementations can be optimized by applying special directives that focus the high-level synthesis (HLS) effort on particular objectives, such as performance, area, throughput, or power consumption  ...  In this paper we examine the benefits of this approach by comparing the performance and design times of HLS generated systems versus custom systems for matrix multiplication.  ...  AN OVERVIEW OF HIGH LEVEL SYNTHESIS TECHNIQUES The overall goal of high level synthesis is to take an algorithm specified in a high level language, extract the control logic (i.e. loops, conditionals,  ... 
doi:10.1109/reconfig.2013.6732298 dblp:conf/reconfig/SkalickyWLR13 fatcat:dk35voxtqbbxzlvb6znraj5zz4

A methodology for synthesis of data path circuits

A. Chowdhary, R.K. Gupta
2002 IEEE Design & Test of Computers  
Acknowledgments We thank Sudhakar Kale, Bobby Wong, Kanchana Sridhar, and William Lock, from Intel, for helping us develop a data path synthesis system based on the methodology presented here.  ...  For instance, the Synopsys Module Compiler 3 lets a designer construct and import a library of predesigned data path blocks (such as adders, multipliers, comparators, and shifters) into a high-level synthesis  ...  The two forms of regularity improve design productivity at different levels.  ... 
doi:10.1109/mdt.2002.1047748 fatcat:cjgri6arnzdrhkjwnp4q7m7dxy

Processor Modeling and Design Tools [chapter]

Prabhat Mishra, Nikil Dutt
2006 Industrial Information Technology  
Time-to-market pressure coupled with short-product lifetimes create a critical need for design automation in processor development.  ...  ., simulators, compilers and debuggers) to enable exploration and validation of candidate architectures.  ...  One of the main purposes of an ADL is to support automatic generation of a high-quality software toolkit including at least an ILP (instruction level parallelism) compiler and a cycle-accurate simulator  ... 
doi:10.1201/9781420007947.ch8 fatcat:azirpu6yajf2dkvpiiqhecdise

Architecture Description Languages [chapter]

Prabhat Mishra, Nikil Dutt
2007 Customizable Embedded Processors  
Modeling plays a central role in design automation of embedded processors.  ...  The language should be powerful enough to capture high-level description of the processor architectures.  ...  Structural ADLs There are two important aspects to consider to design an ADL: level of abstraction versus generality.  ... 
doi:10.1016/b978-012369526-0/50005-x fatcat:rbib63vmazbs3jpezammkjetxm

vlang: Mapping Verilog Netlists to Modern Technologies [article]

Nicholas V. Giamblanco, Andrew Schmidt
2021 arXiv   pre-print
We also explore the usage of vlang as a front-end for high-level synthesis tools.  ...  The remapped design can use the LLVM-framework to target many device technologies such as: x86-64 assembly, RISC-V, ARM or to other PLDs with a modern high-level synthesis tool.  ...  This simultaneously demonstrated vlang's ability to function as a Gate-level simulator and it's ability to retain the exact functionality and cycle accuracy of a hardware design as a software executable  ... 
arXiv:2111.04913v2 fatcat:6jndrg6mufcd7dngi2leidrzby

A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language

A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, H. Meyr
2001 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
From that, software development tools can be generated automatically including high-level language C compiler, assembler, linker, simulator, and debugger frontend.  ...  This article presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language.  ...  automatically HDL code from LISA architecture descriptions in terms of power-consumption, clock speed, and chip area, a gate-level synthesis was carried out.  ... 
doi:10.1109/43.959863 fatcat:dy5amg26prapdghj6a7b66j6c4

Run-time support for dynamically reconfigurable computing systems

Martyn Edwards, Peter Green
2003 Journal of systems architecture  
from many technological drawbacks including the huge configuration overheads of existing reconfigurable devices, the lack of supporting high level software tools, the support of immature compilation tools  ...  The main theme beyond this new technology is to integrate the performance benefits of application specific integrated circuits with the hardware flexibility of programmable processors in a single chip.  ...  In the next approaches that start at the behavioral level. A high-level synthesis technique has also been described that outlines inter-FPGA scheduling at the RTL level.  ... 
doi:10.1016/s1383-7621(03)00068-7 fatcat:weqgn7zw6ndcpggtkwcfcgtj44

A Compiler Infrastructure for FPGA and ASIC Development [article]

John Demme
2020 arXiv   pre-print
By creating a large ecosystem of hardware development tools across vendors, academia, and the open source community, we hope to significantly increase much need productivity in hardware design.  ...  This whitepaper proposes a unified framework for hardware design tools to ease the development and inter-operability of said tools.  ...  Additionally, we have seen the creation of higher-level debuggers, automatic design partitioning, and utilities for automatic synthesis of memory systems and on-chip networks.  ... 
arXiv:2003.00151v1 fatcat:dhpmpbdcbjc67ee5ntgtdcb7qq

Hardware/software partitioning of software binaries

Greg Stitt, Frank Vahid
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
We introduce a new approach that partitions at the software binary level.  ...  We demonstrate that binary-level partitioning yields competitive speedup results compared to source-level partitioning, achieving an average speedup of 1.4 compared to 1.5 for eight benchmarks partitioned  ...  Acknowledgements This work was supported in part by the National Science Foundation (CCR-9876006), UC MICRO, and a Department of Education GAANN fellowship.  ... 
doi:10.1145/774572.774596 dblp:conf/iccad/StittV02 fatcat:nqm4xfwshbdqjpc55unanl72cy
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