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SRAM Read/Write Margin Enhancements Using FinFETs

Andrew Carlson, Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King Liu, Borivoje Nikolic
2010 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes.  ...  The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.  ...  [43] , discuss the yield and optimization of a latch type SRAM sense amplifier, and work in [44] extends that design to a double gated FinFET technology using independent gating.  ... 
doi:10.1109/tvlsi.2009.2019279 fatcat:i3uw4d2evjcezdhycu5b4acbdi

FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices

Alireza Shafaei, Yanzhi Wang, Xue Lin, Massoud Pedram
2014 2014 IEEE Computer Society Annual Symposium on VLSI  
In particular, FinFET devices optimized using advanced device simulators for 7nm process serve as the case study of the paper.  ...  This paper presents FinCACTI, a cache modeling tool based on CACTI which also supports deeply-scaled FinFET devices as well as more robust SRAM cells.  ...  ACKNOWLEDGMENT This research is supported by grants from the PERFECT program of the Defense Advanced Research Projects Agency and the Software and Hardware Foundations of the National Science Foundation  ... 
doi:10.1109/isvlsi.2014.94 dblp:conf/isvlsi/ShafaeiWLP14 fatcat:qmop5naairfddcpxelbg5yltbi

FinFET-based SRAM design

Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolić
2005 Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05  
Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM.  ...  It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty.  ...  With further reductions in bit-line height, the overhead area of sense amplifiers becomes substantial.  ... 
doi:10.1145/1077603.1077607 dblp:conf/islped/GuoBZKN05 fatcat:x23ahqlarrcmjnikxoj5u4ptq4

Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
Designing high-performance and robust sense amplifiers are extremely important for designing SRAM [14] . The voltage mode sense amplifiers are widely used in SRAM design [13] - [15] .  ...  VOLTAGE MODE SENSE AMPLIFIERS The voltage mode sense amplifiers used in the SRAM design can be classified into two categories, namely: 1) current latch sense amplifiers (CLSA) [13] - [15] , [27] and  ...  /FinFET devices, for high-performance logic and memory applications.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky

Low Power Design for Future Wearable and Implantable Devices

Katrine Lundager, Behzad Zeinali, Mohammad Tohidi, Jens Madsen, Farshad Moradi
2016 Journal of Low Power Electronics and Applications  
amplifiers.  ...  Sections 2 and 3 describes the design techniques and challenges in digital and analog domain including a discussion on CMOS and FinFET device characteristics and some basic blocks including memory and  ...  To calculate the access time, a 70 mV bit-line voltage difference from V DD is considered to be sensed by a sense amplifier (SA).  ... 
doi:10.3390/jlpea6040020 fatcat:tf7shjsb25ckjmobfshjrxyqmm

Stochastic Variations in Nanoscale HZO based Ferroelectric finFETs: A Synergistic Approach of READ Optimization and Hybrid Precision Mixed Signal WRITE Operation to Mitigate the Implications on DNN Applications [article]

Sourav De, Md. Aftab Baig, Bo-Han Qiu, Hoang- Hiep Le, Po-Jung Sung, Chun-Jung Su, Yao- Jen Lee, Darsen Lu
2021 arXiv   pre-print
vector-matrix multiplication block for mitigating the impact of stochastic device variations in hafnium zirconium oxide (HZO) based Fe-finFETs.  ...  This paper reports a synergistic approach of READ and WRITE optimization by deploying a high-precision digital computation unit along with a low-precision ferroelectric finFET (Fe-finFETs) based analog  ...  This work was funded by Ministry of Science and Technology grants MOST-108-2634-F-006-008 and MOST-109-2628-E-492 -001 -MY3  ... 
arXiv:2008.10363v3 fatcat:k3xia3cbhrf6xczlylhoofb5vq

Reliable and high performance STT-MRAM architectures based on controllable-polarity devices

Kaveh Shamsi, Yu Bi, Yier Jin, Pierre-Emmanuel Gaillardon, Michael Niemier, X. Sharon Hu
2015 2015 33rd IEEE International Conference on Computer Design (ICCD)  
Source degeneration of access devices in the parallel (P)→ anti-parallel (AP) switching in Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) has ultimately been a limiting factor in the operational  ...  The proposed design offers built-in reliability improvement as it omits one of the available four states in the MLC STT-MRAM memory facilitating the resistance level detection for peripheral circuitry.  ...  current and low leakage in deeply scaled geometries.  ... 
doi:10.1109/iccd.2015.7357123 dblp:conf/iccd/ShamsiBJGNH15 fatcat:bpfkwsfw6fgrvfotgkxaazmimu

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

B.H. Calhoun, Yu Cao, Xin Li, Ken Mai, L.T. Pileggi, R.A. Rutenbar, K.L. Shepard
2008 Proceedings of the IEEE  
As we move forward into the nanoscale regime, circuit design is burdened to Bhide[ more of the problems intrinsic to deeply scaled devices.  ...  ABSTRACT | Well-designed circuits are one key Binsulating[ layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct  ...  Program, in particular, their support of C2S2. They are also grateful to their many faculty and student colleagues in C2S2 for their ideas and inputs on this paper.  ... 
doi:10.1109/jproc.2007.911072 fatcat:dxmkxqiazffjzfv24okubw4zeu

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip

Amir H. Atabaki, Sajjad Moazeni, Fabio Pavanello, Hayk Gevorgyan, Jelena Notaros, Luca Alloatti, Mark T. Wade, Chen Sun, Seth A. Kruger, Huaiyu Meng, Kenaish Al Qubaisi, Imbert Wang (+6 others)
2018 Nature  
By decoupling the formation of photonic devices from transistors, the demonstrated integration approach can achieve many of the goals of multi-chip solutions 5 , with the performance, cost advantage, and  ...  Electronic and photonic technologies have transformed our way of living -from computing and mobile devices, to information technology and the Internet.  ...  Illustration of three major deeply-scaled CMOS processes: planar bulk CMOS, FinFET bulk CMOS, and fully-depleted SOI CMOS. b.  ... 
doi:10.1038/s41586-018-0028-z pmid:29670262 fatcat:722524yrrfarxh7zrsz6ag3aua

Circuit design in nanoscale FDSOI technologies

B. Nikolic, M. Blagojevic, O. Thomas, P. Flatresse, A. Vladimirescu
2014 2014 29th International Conference on Microelectronics Proceedings - MIEL 2014  
Planar fully-depleted SOI technology with ultrathin body and buried oxide presents a platform for an energyefficient design in deeply scaled technologies without major changes in the bulk-CMOS design infrastructure  ...  Overall design optimality is achieved through sensitivity-based optimization by selecting optimal supplies and thresholds.  ...  ACKNOWLEDGEMENT The authors acknowledge students, faculty and members of the Berkeley Wireless Research Center and Soitec.  ... 
doi:10.1109/miel.2014.6842076 fatcat:iamebkiqqvhszgknugw4hlya6m

Reliability Modeling and Mitigation for Embedded Memories

Innocent Okwudili Agbo, Mottaqiallah Taouil, Said Hamdioui
2019 2019 IEEE International Test Conference (ITC)  
Analysis of aging impact on different memory sense amplifiers -The analysis of BTI impact on various memory sense amplifier (SA) designs was performed, while taking into account two BTI models (i.e., Atomistic  ...  The result shows that as technology scales down, the impact of BTI on sensing delay increases, while the sensing voltage decreases, causing less robust and reliable memory sense amplifier.  ...  Therefore, this information can be used by the designers to optimize the design margins of the cell.  ... 
doi:10.1109/itc44170.2019.9000175 dblp:conf/itc/AgboTH19 fatcat:kok7bod22rd7bkxa4aizas65de

III-V-on-Si Transistor Technologies: Performance Boosters and Integration

Daniele Caimi, Heinz Schmid, Thomas Morf, Peter Mueller, Marilyne Sousa, Kirsten Moselund, Cezar Zota
2022 Zenodo  
, device designs and scalability, to name a few.  ...  (c) Benchmark of subthreshold swings for state-of-the-art TFET devices. Figure 4 : 4 Figure 4: Temperature-dependent transfer (a) and subthreshold (b) characteristics of a III-V FinFET devices.  ... 
doi:10.5281/zenodo.6901593 fatcat:wazu4b3v5fai3cemeiuiwr7vra

Silicon-integrated uncooled infrared detectors: Perspectives on thin films and microstructures

V. R. Mehta, S. Shet, N. M. Ravindra, A. T. Fiory, M. P. Lepselter
2005 Journal of Electronic Materials  
This paper reviews challenges of materials, microstructures, interfaces, and reactions of thin-film materials and technologies posed by such applications.  ...  ACKNOWLEDGEMENTS The authors acknowledge assistance from TMS, New Jersey Institute of Technology, Integron Solutions, BTL Fellows, and Lucent Technologies.  ...  Nanotechnology is implemented, for example, by finfet transistor designs that enable the manufacturability of aggressive highperformance design rules.  ... 
doi:10.1007/s11664-005-0055-z fatcat:7phyk2ka4vbxtb7zebluegm7ou

Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors

Yunfei Gu, Dengxue Yan, Vaibhav Verma, Pai Wang, Mircea Stan, Xuan Zhang
2018 Journal of Low Power Electronics and Applications  
Energy-efficient microprocessors are essential for a wide range of applications.  ...  While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/jlpea8030028 fatcat:ny4cuxcc2nhyvnltui7md6wnmu

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang
2012 IEEE Journal of Solid-State Circuits  
The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V around/above 1.0 V.  ...  His research interests include noise suppression design technologies, embedded measurement circuit design, and ultra-low-power SRAM design. Jihi-Yu  ...  A full-swing large signal Sense Amplifier (SA) is used to capture the BL voltage for robust Read operation.  ... 
doi:10.1109/jssc.2012.2187474 fatcat:acydfavabfebdjgozk5bwawujm
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