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Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities

M.T. Schmitz, B.M. Al-Hashimi, P. Eles
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Based on the key observation that operational modes are executed with different probabilities, i.e., the system spends uneven amounts of time in the different modes, we develop a new co-design technique  ...  In particular we concentrate on distributed embedded systems that accommodate several different applications within a single device, i.e., multi-mode embedded systems.  ...  6 : 6 Multi-Mode Embedded Systems Design Flow design flow is primarily based on two nested optimization loops.  ... 
doi:10.1109/tcad.2004.837729 fatcat:a2enjz5p7jci7m3j2mjkegnk5e

Model Based Design Environment for Data-driven Embedded Signal Processing Systems1

Kishan Sudusinghe, Inkeun Cho, Mihaela van der Schaar, Shuvra S. Bhattacharyya
2014 Procedia Computer Science  
We demonstrate the utility of our proposed new design methods on an energy-constrained, multi-mode face detection application.  ...  Due to critical application constraints on energy consumption, real-time performance, computational resources, and core application accuracy, the design spaces for such applications are highly complex.  ...  In particular, the "mode-level schedules" that are are used to execute specific application modes under specific mode parameter settings are not part of the DHMM framework specification.  ... 
doi:10.1016/j.procs.2014.05.107 fatcat:llt6dkm3aval3hdgijfb74w77a

Architectural design features of a programmable high throughput AES coprocessor

A. Hodjat, P. Schaumont, I. Verbauwhede
2004 International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004.  
Programmable, high throughput domain specific crypto processors are required for different networking applications.  ...  Our design is a loosely coupled, independently working crypto-coprocessor that runs AES in ECB, CBC-MAC, Counter, and CCM modes of operation at a maximum throughput of 3.43 Gbits/s in a 0.18-ȝm CMOS technology  ...  Instead, we propose the design of programmable, multi-gigabits/s domain specific coprocessors to obtain the required throughput.  ... 
doi:10.1109/itcc.2004.1286703 dblp:conf/itcc/HodjatSV04 fatcat:dshi4k2jqzgwjkwovoy5bimrx4

Energy Efficient Multi-Core Processing

Charles Leech, Tom J. Kazmierski
2014 Electronics  
concept of minimal architecture synthesis and how it can be used to produce an application specific, energy efficient processor.  ...  The principles of the picoMIPS processor are illustrated with an example of the discrete cosine transform (DCT) and inverse DCT (IDCT) algorithms implemented in a multi-core context to demonstrate the  ...  ACKNOWLEDGMENT This work was supported by the Engineering and Physical Sciences Research Council (EPSRC), UK under grant number EP/K034448/1 " PRiME: Power-efficient, Reliable, Many-core Embedded systems  ... 
doi:10.7251/els1418003l fatcat:ehztmbwggvayddswnnp6qxg2ra

Towards design and validation of mixed-technology SOCs

S. Mir, B. Charlot, G. Nicolescu, P. Coste, F. Parrain, N. Zergainoh, B. Courtois, A. Jerraya, M. Rencz
2000 Proceedings of the 10th Great Lakes Symposium on VLSI - GLSVLSI '00  
A high level multilanguage/multi-engine approach is used for system specification and co-simulation.  ...  In particular, applications based on fingerprint recognition are considered since a rich variety of sensors and data processing algorithms can be considered.  ...  This paper illustrates one possible way of addressing this by means of a multi-language/multi-engine simulation for high level system design and validation, and one single-language/single-engine simulation  ... 
doi:10.1145/330855.330950 dblp:conf/glvlsi/MirCNCPZCJR00 fatcat:awxvh2hsazcfrjawmc34nj3r4y

An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

Xinyu Li, Omar Hammami
2009 International Journal of Reconfigurable Computing  
Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements.  ...  An automatic design flow is proposed well suited for data flow signal processing exhibiting both pipelining and data parallel mode of execution.  ...  Finally system bit file is downloaded to multi-FPGA platform and application is executed. High Level Synthesis: C-Based.  ... 
doi:10.1155/2009/631490 fatcat:kcrbtxmc7jgd3jptwwrxqcuqf4

Hardware-dependent Software synthesis for many-core embedded systems

Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski
2009 2009 Asia and South Pacific Design Automation Conference  
The generated HdS methods provide a library of application level services to the C processes on individual SW cores.  ...  Synthesis results for an multi-core MP3 decoder design, using ESE, show that the HdS is generated in order of seconds, compared to hours of manual coding.  ...  ACKNOWLEDGMENTS This work builds on several years of system level design research in Embedded Systems Methodology Group (ESMG) at Center for Embedded Computer Systems (CECS), UC Irvine.  ... 
doi:10.1109/aspdac.2009.4796498 dblp:conf/aspdac/AbdiSVCHLG09 fatcat:rlru6o6qpffjzmchgth36b4pd4

Virtual Manycore platforms: Moving towards 100+ processor cores

R Leupers, L Eeckhout, G Martin, F Schirrmeister, N Topham, Xiaotao Chen
2011 2011 Design, Automation & Test in Europe  
These platforms are heterogeneous, homogeneous, or a mixture of subsystems of both types, both relatively generic and quite application-specific. They are applied to many different application areas.  ...  When we consider the design, verification, software development and debugging requirements for applications on these platforms, the need for virtual platform technologies for Manycore systems grows quickly  ...  multi-threading of multi-core simulations based on that single-core engine.  ... 
doi:10.1109/date.2011.5763121 dblp:conf/date/LeupersEMSTC11 fatcat:tszobn6thbhmpo7b2ow37xiwoe

Accelerating Image Algorithm Development using Soft Co-Processors on FPGAs

Tiantai Deng, Danny Crookes, Roger Woods, Fahad Siddiqui
2018 2018 29th Irish Signals and Systems Conference (ISSC)  
In this paper, we present a system model based on a set of Soft Co-Processors, each of which implements a basic image-level operation (or a common combination of such operations) based on the high-level  ...  For creating function-specific Co-processors using our macro-based tool, the overheads compared with an expert hardware design are around 20%.  ...  Current tools to accelerate the design process on FPGAs There are many high level synthesis (HLS) tools which aim to accelerate the design process on FPGAs.  ... 
doi:10.1109/issc.2018.8585363 fatcat:vpvnkfcz5zgz5p32fltkltx4zq

Architectural Optimizations for Text to Speech Synthesis in Embedded Systems

Soumyajit Dey, Monu Kedia, Anupam Basu
2007 2007 Asia and South Pacific Design Automation Conference  
In this work, the performance of a Text to Speech Synthesis application is evaluated on embedded processor architectures and modifications in the underlying hardware platform are proposed for real time  ...  However, the real-time performance of such applications in handheld platforms with on-line incoming text streams have not been explored till date.  ...  Design of a speech synthesis ASIC, based on the line spectrum pair (LSP) scheme can be found in [7] .  ... 
doi:10.1109/aspdac.2007.358002 dblp:conf/aspdac/DeyKB07 fatcat:aysxrnizdvac7ahf76cmt7lraa

High-throughput programmable cryptocoprocessor

A. Hodjat, I. Verbauwhede
2004 IEEE Micro  
Combining programmability with high throughput supports a wide range of current and future standards for security applications. A high-speed CPU is one way to implement security primitives.  ...  High-speed Internet Protocol security (IPsec) applications require high throughput and flexible security engines.  ...  Acknowledgments This article is based on work supported by the Space and Naval Warfare Systems Center, San Diego, under contract N66001-02-1-8938.  ... 
doi:10.1109/mm.2004.11 fatcat:z46xetlq2re65hojayvlm3daoa

A design methodology for space-time adapter

Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
2007 Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07  
In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters  ...  This paper presents a solution to efficiently explore the design space of communication adapters.  ...  Moreover, we also investigate the use of a STAR architecture in high-level synthesis flow: in our flow we use scheduling information -available from a high level synthesis tool-about data accesses and  ... 
doi:10.1145/1228784.1228868 dblp:conf/glvlsi/ChavetCUM07 fatcat:2v4zratr4vgrza7zkozd4l7qii

A Systematic Method for Hardware Software Codesign using Vivado HLS

2019 International journal of recent technology and engineering  
An overview of vivado design suite is illustrated with configuration, implementation, detailed implementation, summary, settings along with component name.  ...  Improved productivity results are indicated through simulation, synthesis, implementation, bitstream generation.  ...  Very High Level Synthesis for Image Processing Applications (YanjingBI et.al., 2016) this paper aims to produce effective model for FPGA designs in Matlab environment by using very high level synthesis  ... 
doi:10.35940/ijrte.d7008.118419 fatcat:4zfv2o6c75amjeadsgwrowsirm

Cover and Frontmatter

2008 2008 International Conference on Application-Specific Systems, Architectures and Processors  
6: New Directions in Application-Specific Design ............................ 132 • Managing Multi-Core Soft-Error Reliability Through Utility-driven Cross Domain Optimization ........................  ...  across multi-mode H.264 decoders .................................................................................................... 287 • An FPGA Architecture for CABAC Decoding in Many-core Systems  ... 
doi:10.1109/asap.2008.4580202 fatcat:ylw2sim6gnb2hbh3qjnkbcepwu

Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator

Eduardo André Neves
2018 Journal of Computers  
This article presents the analysis and comparison of two powerful tools to explore design space and study multi-core microprocessors.  ...  levels of abstraction.  ...  Chisel can generate Verilog, which is a lower level language, allowing either FPGA emulation or application specific integrated circuit (ASIC) synthesis.  ... 
doi:10.17706/jcp.13.5.555-563 fatcat:i4km2rnotfcpbgd7eqci6o6d6a
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