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Design of memory efficient FIFO-based merge sorter

Youngil Kim, Seungdo Choi, Yong Ho Song
2018 IEICE Electronics Express  
When implemented in hardware, a FIFO-based merge sorters often shows excellent hardware resource utilization efficiency but requires high buffer memory usage.  ...  In this paper, we presents a cost-effective hardware architecture of a FIFO-based merge sorter. Our proposed architecture minimizes buffer memory requirement.  ...  Section 2 briefly describes the structure of a FIFO-based merge sorter and cascading FIFO-based merge sorter.  ... 
doi:10.1587/elex.15.20171272 fatcat:drgmfdv3qjfslguveflbw5kxcy

A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism

2017 IEICE transactions on information and systems  
In this paper, we present an FPGA-based sorting accelerator combining Sorting Network and Merge Sorter Tree, which is customizable by means of tuning design parameters.  ...  However, this result is limited because of insufficient memory bandwidth.  ...  The FIFO consists of internal memory resources (hard macros) of the FPGA, and Fig. 19 The data emitted from the merge sorter tree is sequentially written into the head of the Write Area, without (a)  ... 
doi:10.1587/transinf.2016edp7383 fatcat:6vxnbsi3hjdopav56dpcdsyfee

Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA

Ren Chen, Sruja Siriyal, Viktor Prasanna
2015 Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '15 Applications of Sorting Algorithm Online social networks Citation networks Protein interactions Air traffic network WWW Neural network  Parallel sorting network with simple control  ...  Torresen)  Tree merge sorterFIFO-based merge sorter  Insertion sorterFIFO & Tree  2 GB/s using on-chip memory Tree merge sorter FIFO-based merge sorter Insertion sorter Related Work  ...  Olukotun) Memory and Energy Efficient Mapping  Drawbacks of the state-of-the-art  High throughput not guaranteed  Design scalability needs to be improved  No analysis provided  Data parallelism  ... 
doi:10.1145/2684746.2689068 dblp:conf/fpga/ChenSP15 fatcat:3jzyfd3sifgpbcg33x5dhfmikm

Optimal Parallel Hardware K-Sorter and Top K-Sorter, with FPGA Implementations

Naoyuki Matsumoto, Koji Nakano, Yasuaki Ito
2015 2015 14th International Symposium on Parallel and Distributed Computing  
This paper presents a FIFO-based parallel merge sorter optimized for the latest FPGA. More specifically, we show a sorter that sorts K keys in latency K +log 2 K −1 using log 2 K comparators.  ...  The implementation results show that our K-sorter reduces the used memory resources by half, and both K-sorter and topK-sorter are practical and efficient.  ...  We then show memory efficient implementations of K-sorter and topK-sorter. Let us design K-merger/M , which uses FIFOs of size M . We first assume that M ≤ K.  ... 
doi:10.1109/ispdc.2015.23 dblp:conf/ispdc/MatsumotoNI15 fatcat:vezo3hc455hzbjfoganrdlx2xe

Accelerating Random Forest training process using FPGA

Chuan Cheng, Christos-Savvas Bouganis
2013 2013 23rd International Conference on Field programmable Logic and Applications  
Key to the above gains is a novel FPGA FIFO based merge sorter module, a core component in the architecture, that exhibits high efficiency in memory utilisation; as well as a batch training strategy that  ...  enable full exploitation of the high memory bandwidth offered by the on-chip memory featured on FPGA devices.  ...  Efficient FIFO based merge sorter The FIFO based merge sorter features fast output throughput and low resource utilization and is considered one of the most appropriate sorter type for FPGA devices [15  ... 
doi:10.1109/fpl.2013.6645500 dblp:conf/fpl/ChengB13 fatcat:qhwhtjln6rbwniyomejhb5syry

In-memory database acceleration on FPGAs: a survey

Jian Fang, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, H. Peter Hofstee
2019 The VLDB journal  
Therefore, this paper surveys using FPGAs to accelerate in-memory database systems targeting designs that can operate at the speed of main memory.  ...  Ease of programming is improving through support of shared coherent virtual memory between the host and the accelerator, support for higher-level languages, and domain-specific tools to generate FPGA designs  ...  FIFO merge sorter The first-in first-out FIFO merge sorter is a sorter that can merge two pre-sorted streams into a large one. The key element is the select-value unit.  ... 
doi:10.1007/s00778-019-00581-w fatcat:32edtb7frfh3xhpziks75lys3y

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2017 IPSJ Transactions on System LSI Design Methodology  
However, developing an FPGA-based system is challenging because the complexity of the hardware and software co-design.  ...  First, we adopt a shell-and-IP design pattern to improve the reusability and the portability of accelerator designs.  ...  Merge-sorter Sorting is a fundamental task in computer science. Software sorters are implemented in almost all programming environments.  ... 
doi:10.2197/ipsjtsldm.10.63 fatcat:z3psr3xj2rbetht67iyjqhvq4m

A Versatile Linear Insertion Sorter Based on a FIFO Scheme

Roberto Perez-Andrade, Rene Cumplido, Fernando Martin Del Campo, Claudia Feregrino-Uribe
2008 2008 IEEE Computer Society Annual Symposium on VLSI  
A linear sorter based on a First-In First-Out (FIFO) scheme is presented.  ...  Results of synthesizing the proposed architecture targeting a Field Programmable Gate Array (FPGA) are presented and compared against other reported hardware based sorters.  ...  In this work, a compact and efficient hardware implementation of a linear sorter based on a FIFO scheme was presented.  ... 
doi:10.1109/isvlsi.2008.14 dblp:conf/isvlsi/Perez-AndradeCCU08 fatcat:zjhlb6zurrh6jkvpee5hlklfxq

FLiMS: Fast Lightweight Merge Sorter

Philippos Papaphilippou, Chris Brooks, Wayne Luk
2018 2018 International Conference on Field-Programmable Technology (FPT)  
We have developed a highly-efficient and simple parallel hardware design for merging two sorted lists residing in banked (or multi-ported) memory.  ...  Our solution uses a modified version of the bitonic merge block, as found in a bitonic sorter, repurposed for performing parallel merge for streaming data.  ...  The support of the United Kingdom EPSRC (grant number EP/I012036/1, EP/L00058X/1, EP/L016796/1, EP/N031768/1 and EP/K034448/1), European Union Horizon 2020 Research and Innovation Programme (grant number  ... 
doi:10.1109/fpt.2018.00022 dblp:conf/fpt/PapaphilippouBL18 fatcat:yimiidhh4jc3bpxracyus735c4

FLiMS: a Fast Lightweight 2-way Merger for Sorting [article]

Philippos Papaphilippou, Wayne Luk, Chris Brooks
2022 arXiv   pre-print
In this paper, we present FLiMS, a highly-efficient and simple parallel algorithms for merging two sorted lists residing in banked and/or wide memory.  ...  Also presented are efficient variations of FLiMS for optimizing throughput for skewed datasets, achieving stable sorting or using fewer dequeue signals.  ...  The support of Microsoft and the United Kingdom EPSRC (grant number EP/L016796/1, EP/I012036/1, EP/L00058X/1, EP/N031768/1 and EP/K034448/1), European Union Horizon 2020 Research and Innovation Programme  ... 
arXiv:2112.05607v3 fatcat:vsljd4t3xzferlfac2y4kz2msq

Sorting on architecturally diverse computer systems

Roger D. Chamberlain, Narayan Ganesan
2009 Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications - HPRCTA '09  
Here, we explore the design space of sorting algorithms in reconfigurable hardware, looking to maximize the benefit associated with high-bandwidth, multiple-port access to memory.  ...  Sorting is an important problem that forms an essential component of many high-performance applications.  ...  With the infeasibility of the memory array sort algorithm, we will concentrate on the use of the systolic array sorter.  ... 
doi:10.1145/1646461.1646466 dblp:conf/sc/ChamberlainG09 fatcat:lkqn77pp6rg7lnkrvxv4webtii

An Efficient VLSI Architecture for Adaptive Rank Order Filter for Image Noise Removal

M. Hanumantharaju
2011 International Journal of Information and Electronics Engineering  
In this paper, an Efficient Very Large Scale Integration (VLSI) Architecture and Field Programmable Gate Array (FPGA) implementation of Adaptive Rank Order Filter (AROF) is proposed.  ...  The expansion of the window size in an AMF is based on whether the median is noisy or not. However, this criterion is not an appropriate when the noise density is moderate or high.  ...  sequence A Batcher's odd-even merge sorting network is based on sorting two halves of the input sequence.  ... 
doi:10.7763/ijiee.2011.v1.14 fatcat:2osxmsksynaqpobxevpvuqz3zi

A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder

Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee
2012 IEEE Journal of Solid-State Circuits  
Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with energy efficiency of 0.024 nJ/bit/proc.  ...  Furthermore, a novel hybrid-partitioned FIFO is proposed to provide sufficient memory bandwidth to processing units and alleviate power consumption.  ...  ACKNOWLEDGMENT The authors would like to thank UMC for fabrication of the test chip, Chip Implementation Center for providing the CAD tools and measurement equipment, and ATU program-eNES.  ... 
doi:10.1109/jssc.2012.2185193 fatcat:yppbcasvqfbsddxux6li2rmgg4

Bitonic Sorting on Dynamically Reconfigurable Architectures

J. Angermeier, E. Sibirko, R. Wanka, J. Teich
2011 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum  
We present a detailed description of the design and actual implementation, and we present experimental results of our approach to show its benefits in performance and the trade-offs of our approach.  ...  Sorting is one of the most investigated tasks computers are used for.  ...  It is based on the classical sorting-by-merging algorithm that merges two sorted halves of a sequence to a completely sorted sequence.  ... 
doi:10.1109/ipdps.2011.164 dblp:conf/ipps/AngermeierSWT11 fatcat:wkusx2k5evfqdceioxsteozyfu

Designing hardware with dynamic memory abstraction

Jiri Simsa, Satnam Singh
2010 Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10  
This opens up a space for the use of dynamic memory abstraction in high-level synthesis. In this paper, we explain how to design hardware using C programs with malloc() and free().  ...  Recent progress in program analysis has produced tools that are able to compute upper bounds on the use of dynamic memory.  ...  The interface of these FIFOs consists of two methodsint deq(FIFO fifo) and void enq(FIFO fifo, int data) -with the standard functionality.  ... 
doi:10.1145/1723112.1723125 dblp:conf/fpga/SimsaS10 fatcat:xusuun2wpjcibetroopkg4zaee
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