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Design of an Online Testable Ternary Circuit from the Truth Table [chapter]

Noor M. Nayeem, Jacqueline E. Rice
2013 Lecture Notes in Computer Science  
This paper presents a new approach for converting a ternary reversible circuit implemented from a truth table into an online testable circuit.  ...  Preliminary work shows fault coverage of 84.89% when the approach is applied to a testable ternary half adder.  ...  Conclusion We have introduced a technique that takes a ternary reversible circuit generated as described in [10] and transforms the circuit into an online testable circuit.  ... 
doi:10.1007/978-3-642-36315-3_12 fatcat:c7dxvem5mrg6tgm7gzj4nkfbbm

On designing a ternary reversible circuit for online testability

Md. R. Rahman, J. E. Rice
2011 Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing  
This paper details work on designing an online testable block for ternary reversible logic. We build on earlier work that introduced the basic design, and provide some improvements and modifications.  ...  The proposed testable block can be used to implement most ternary logic operations and is capable of testing the reversible ternary network in real time (online).  ...  Acknowledgment This research was funded by a grant from the Natural Sciences and Engineering Research Council of Canada (NSERC).  ... 
doi:10.1109/pacrim.2011.6032878 fatcat:gsiid6rzpbeitjj7sbuivnt4sy

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies

Himanshu Thapliyal, Nagarajan Ranganathan
2012 2012 IEEE Computer Society Annual Symposium on VLSI  
Nagarajan Ranganathan to allow me to work on the burgeoning area of reversible logic and emerging nanotechnologies.  ...  DEDICATION This dissertation is lovingly dedicated to my mother for all the sacrifices she made to ensure that I obtain the best education possible. ii ACKNOWLEDGEMENTS I would like to thank my doctoral  ...  circuit into an online testable circuit that can detect online any single-bit errors, including soft errors in the logic blocks is presented.  ... 
doi:10.1109/isvlsi.2012.83 dblp:conf/isvlsi/ThapliyalR12 fatcat:vqp3ruke4fa5vkacwfoeehaseu

PERFORMANCE ANALYSIS OF SRAM CELL USING REVERSIBLE LOGIC GATES

BUKYA BALAJI
2019 Figshare  
Reversible logic shows a great potentialin the design of Low-power circuits.  ...  Remarkable workhas been done in design of basic arithmetic circuits.Present day progress in sequential circuit design ofreversible logic circuits has shown new ways inperformance of Static random access  ...  At the time of write operation, the table 1 shows the truth table of access transistors.  ... 
doi:10.6084/m9.figshare.7660355.v1 fatcat:gbxwzurpmzeqpgn6zx73ug6ipi

Fastest classes of linearly independent transforms over GF(3) and their properties

B.J. Falkowski, C. Fu
2005 IEE Proceedings - Computers and digital Techniques  
The number of required additions and multiplications in new LI transforms is lower when compared with the ternary Reed -Muller transform, which was previously known as the most efficient transform over  ...  Experimental results in one class of fastest LI transforms for some ternary benchmark functions are also shown here and compared with those of the fixed polarity Reed -Muller transform over GF(3).  ...  They are of great interest because the Reed -Muller based circuits have many desirable properties, such as simple testability vectors [11] .  ... 
doi:10.1049/ip-cdt:20045162 fatcat:daiznc4uk5ccffks7lqub3dliu

SCIENCE & TECHNOLOGY

Hari Gaur, Ashutosh Singh, Umesh Ghanekar
2016 Pertanika J. Sci. & Technol   unpublished
This paper provides a comparative study of online testability for reversible logic.  ...  We bring together a review of fault models, performance parameters and online testing strategies from the literature with the aim of obtaining a near optimal solution by efficiently exploring the entire  ...  An online testable circuit was constructed from a Toffoli circuit in similar manner except for the second step where, first a Toffoli gate was converted into an ETG connected to an additional parity line  ... 
fatcat:o6j52tkakfg4flvnft2xu7jb5a

Subject index volumes 1–200

1999 Theoretical Computer Science  
table, 8 query machines, 153 I truth values, 949, 3630 of predicate variables, 703 truth-table complete, 926 completeness, 1049 programs, 509 reducibilities in NP, 3130 reducibility, 607 reducibility  ...  counting -, 970 hook -, 2259 of automata, 382 powers of -, 2713 structure of -, 382 generating graph languages, 982 generating graphs, 613 from graphs, 613 generating Hamiltonian circuits, 2513  ... 
doi:10.1016/s0304-3975(98)00319-3 fatcat:s22ud3iiqjht7lfbtc3zctk7zm

Ideal Systems, Ideal Technology and their Realization Opportunities Using Information Communication & Computation Technology (ICCT) and Nanotechnology (NT)

P. Sreeramana Aithal
2021 Zenodo  
Technology management is an area of predicting, identifying, managing, and utilising existing and new technologies for the benefit of people, organizations, and society.  ...  It is believed that the performance of a system and the capability of a technology can be continuously improved by means of comparing their properties with the properties of ideal system or ideal technology  ...  Green technologies support the use of natural  ... 
doi:10.5281/zenodo.4709634 fatcat:bvx7d7aax5aatnlayvnhuaozke

D2.1 Vision, State of the Art and Requirements Analysis

Striccoli Domenico
2019 Zenodo  
The main objectives of this deliverable are (i) to describe the project vision, the applicability scenarios, and demonstration use cases; (ii) to perform an analysis of the State of the Art and current  ...  market solutions; (iii) to identify and describe the technical and architectural requirements of the GUARD framework.  ...  However, the flexibility of P4 leverages more advanced hardware technology, namely dedicated © GUARD 2019 Page 58 of 128 processing architectures or reconfigurable match tables as an extension of Ternary  ... 
doi:10.5281/zenodo.3564301 fatcat:lrb6r6zat5bk5oqwpwwlui3ztm

D2.1 Vision, State of the Art and Requirements Analysis

Striccoli Domenico
2019 Zenodo  
The main objectives of this deliverable are (i) to describe the project vision, the applicability scenarios, and demonstration use cases; (ii) to perform an analysis of the State of the Art and current  ...  market solutions; (iii) to identify and describe the technical and architectural requirements of the GUARD framework.  ...  However, the flexibility of P4 leverages more advanced hardware technology, namely dedicated processing architectures or reconfigurable match tables as an extension of Ternary Content-Addressable Memories  ... 
doi:10.5281/zenodo.4268474 fatcat:vtvogbwapzdc7nn6vms2cvdjou

Power pulsing of the CALICE tile hadron calorimeter

Mathias Reinecke
2016 2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD)  
DUNE consists of an intense neutrino beam fired a distance of 1300 km from Fermilab (near Chicago) to the 40,000 ton Liquid Argon DUNE detector, located deep underground in the Homestake mine.  ...  In this talk I will describe the scientific aims of DUNE, focussing on the experimental challenges in constructing an operating very large liquid argon time projection chamber detectors.  ...  N25-5: Design of the ATLAS New Small Wheel Gas Leak Tightness Station for the Micromegas Detector Modules Acknowledgments: This work was partially supported by project PTDC/FIS-NUC/2525/2014 through COMPETE  ... 
doi:10.1109/nssmic.2016.8069748 fatcat:zjgd7dmfdbhntb4kfwdtrlejhi

Cognitive Literary Studies: Current Themes and New Directions

2013 Poetics Today  
of shared emotive and cognitive principles.  ...  The volumes published in this series represent both specialized scholarship and interdisciplinary investigations that are deeply sensitive to cultural specifics and grounded in a cross-cultural understanding  ...  that one can design an experiment of the X: A, B, C form.  ... 
doi:10.1215/03335372-2389659 fatcat:b2dzja55ljdd7d7wxhcxatwnkq

Multi-level simulation of nano-electronic digital circuits on GPUs [article]

Eric Schneider, Universität Stuttgart, Universität Stuttgart
2019
Simulation of circuits and faults is an essential part in design and test validation tasks of contemporary nano-electronic digital integrated CMOS circuits.  ...  However, due to the rising complexity of the circuit behavior and the steady growth of the designs with respect to the transistor count, timing-accurate simulation of current designs requires a lot of  ...  Truth tables of gates as well as intermediate signal values are kept in the local shared memory, while inputs and outputs of the clusters are stored in the device memory.  ... 
doi:10.18419/opus-10483 fatcat:xc2ua5u4ivcnbhkq57hztefiku

Age Related Changes During Adulthood in Cognitive Processes Reliant on the Pre-Frontal Cortex: Attention, Inhibitory Control, Working Memory and Relational Processing

Jo-Anne Todd, University, My, Glenda Andrews
2018
It was administered to a sample of 125 normally ageing adults who ranged in age from 18 years to 92 years with all age decades represented.  ...  The test battery of 16 tasks assessed these constructs as well as speed of processing, crystallized and fluid intelligence, and frontal functioning (Tower of London).  ...  functional and testable model of cognitive ageing.  ... 
doi:10.25904/1912/1986 fatcat:xveqkkqwh5cbvodnmc3kxli7ma

The elements of hybrid electrical system diagnosis [article]

Howard J. Jelinek, University Of Canterbury
2011
Furthermore, by knowing a priori how a fault will affect output signals, the engineer can design programmed equipment which will automatically monitor the system signals and detect the occurrence of a  ...  During the draft stages of this thesis, each chapter was written to "stand alone". Unfortunately repetition has not been completely eliminated from [...]  ...  The usual proof is the truth table method (Figure 3 .. 8 is a truth table) and from Figure 3.8 we have the following: logical proposition is associated with each Be line, then a logical 1 on the line  ... 
doi:10.26021/1619 fatcat:jkzode733be4rmov2a7xsokx4i
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