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Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits

H. Goudarzi, M. J. Dousti, A. Shafaei, M. Pedram
2014 Quantum Information Processing  
This paper presents a physical mapping tool for quantum circuits, which generates the optimal Universal Logic Block (ULB) that can perform any logical fault-tolerant (FT) quantum operations with the minimum  ...  In addition to the quantum physical mapper, an approach is presented to determine the single best ULB size for a target quantum circuit by examining the latency of different FT quantum operations mapped  ...  Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright annotation thereon.  ... 
doi:10.1007/s11128-013-0725-3 fatcat:aq7sqkry7va3pc4gm47fvcbuxq

A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation [article]

Tzvetan S. Metodi , Frederic T. Chong University of California at Davis, Massachusetts Institute of Technology)
2005 arXiv   pre-print
We propose a Quantum Logic Array (QLA) microarchitecture that forms the foundation of such a system.  ...  We leverage the extensive groundwork in quantum error correction theory and provide analysis that shows that our system is both asymptotically and empirically fault tolerant.  ...  Acknowledgements: This work is supported in part by the DARPA QUIST program, in part by a NSF CAREER grant and a UC Davis Chancellor's Fellowship awarded to Fred Chong, and in part by the NSF Center for  ... 
arXiv:quant-ph/0509051v1 fatcat:rinkzytwdnfwbf3bavhizofj3q

Demonstration of fault-tolerant universal quantum gate operations [article]

Lukas Postler, Sascha Heußen, Ivan Pogorelov, Manuel Rispler, Thomas Feldker, Michael Meth, Christian D. Marciniak, Roman Stricker, Martin Ringbauer, Rainer Blatt, Philipp Schindler, Markus Müller (+1 others)
2021 arXiv   pre-print
Here, we demonstrate a fault-tolerant universal set of gates on two logical qubits in a trapped-ion quantum computer.  ...  This requires that all operations on the quantum register obey a fault-tolerant circuit design which, in general, increases the complexity of the implementation.  ...  Here, we demonstrate a fault-tolerant universal set of gates on two logical qubits in a trapped-ion quantum  ... 
arXiv:2111.12654v2 fatcat:l5tlg5xtfzc5bntttsgm2tsbxq

High-level interconnect model for the quantum logic array architecture

Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong
2008 ACM Journal on Emerging Technologies in Computing Systems  
The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a  ...  The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution  ...  any universal set of operations.  ... 
doi:10.1145/1330521.1330522 fatcat:pz3wuk4qwnbplpzksc7pzqgj24

Hybrid architecture for encoded measurement-based quantum computation

M. Zwerger, H. J. Briegel, W. Dür
2014 Scientific Reports  
We present a hybrid scheme for quantum computation that combines the modular structure of elementary building blocks used in the circuit model with the advantages of a measurement-based approach to quantum  ...  The emphasis of our approach lies on (fault-tolerant) measurement-based realization of quantum error correction and the manipulation of encoded quantum information.  ...  Raussendorf for helpful comments on an earlier version of the manuscript. This work was supported by the Austrian Science Fund (FWF): P24273-N16, SFB F40-FoQus F4012-N16.  ... 
doi:10.1038/srep05364 pmid:24946906 pmcid:PMC4064337 fatcat:k2mgqbcswjd6tgzrok6b2jtvfu

A layered software architecture for quantum computing design tools

K.M. Svore, A.V. Aho, A.W. Cross, I. Chuang, I.L. Markov
2006 Computer  
instructions and circuits with added fault tolerance and sufficient parallelism.  ...  Compilers and computer-aided design tools are essential for fine-grained control of nanoscale quantum-mechanical systems.  ...  Acknowledgments We are grateful to Stephen Edwards for many helpful comments on computer-aided design flows.  ... 
doi:10.1109/mc.2006.4 fatcat:xshlid4hpbaydkolw3cajbx7ai

Large-scale modular quantum-computer architecture with atomic memory and photonic interconnects

C. Monroe, R. Raussendorf, A. Ruthven, K. R. Brown, P. Maunz, L.-M. Duan, J. Kim
2014 Physical Review A. Atomic, Molecular, and Optical Physics  
We show that this architecture can be made fault-tolerant, and demonstrate its viability for fault-tolerant execution of modest size quantum circuits.  ...  We analyze a modular ion trap quantum computer architecture with a hierarchy of interactions that can scale to very large numbers of qubits.  ...  Circuit diagram for realizing fault-tolerant Toffoli gate using Steane code.  ... 
doi:10.1103/physreva.89.022317 fatcat:rqrcjwi2xfgllbkyxcz7ltbmny

Transversality and lattice surgery: Exploring realistic routes toward coupled logical qubits with trapped-ion quantum processors

M. Gutiérrez, M. Müller, A. Bermúdez
2019 Physical Review A  
In addition to the demonstration of the beneficial role of the encoding, a break-even point in the progress towards large-scale quantum computers will be the implementation of a universal set of gates.  ...  We present a detailed comparative study of two alternative strategies for trapped-ion topological color codes, either a transversal or a lattice-surgery approach, characterized by a detailed microscopic  ...  Furthermore, for a fault-tolerant procedure on a distance-3 code, any single fault is correctable, so error configurations of weight-1 will never result in a logical error.  ... 
doi:10.1103/physreva.99.022330 fatcat:nra6pwrny5bmbp23b4rqtypp44

Hybrid architecture for encoded measurement-based quantum computation [article]

M. Zwerger, H.J. Briegel, W. Dür
2013 arXiv   pre-print
We present a hybrid scheme for quantum computation that combines the modular structure of elementary building blocks used in the circuit model with the advantages of a measurement-based approach to quantum  ...  The performance of the scheme is determined by the quality of the resource states, where within this error model we find a threshold of the order of 10% local noise per particle for fault-tolerant quantum  ...  In particular, we obtain a fault-tolerant quantum memory and code switcher, and a scheme for long-distance quantum communication.  ... 
arXiv:1308.4561v1 fatcat:xavhwccqzne2reqmk7fuodw4fy

Towards Demonstrating Fault Tolerance in Small Circuits Using Bacon-Shor Codes [article]

Ariel Shlosberg, Anthony M. Polloreno, Graeme Smith
2021 arXiv   pre-print
Additionally, several works have explored the implementation of logical gates[3-5]. In this work we study a next step - fault-tolerantly implementing quantum circuits.  ...  This provides a concrete suggestion for a small-scale fault-tolerant demonstration of a quantum algorithm that could be accessible with existing hardware.  ...  Department of Energy, Office of Science, National Quantum Information Science Research Centers, Quantum Systems Accelerator (QSA). AMP is funded under NSF grant number 1734006.  ... 
arXiv:2108.02079v1 fatcat:qjuceffeebg57a537d57fqspti

Resource requirements for fault-tolerant quantum simulation: The ground state of the transverse Ising model

Craig R. Clark, Tzvetan S. Metodi, Samuel D. Gasster, Kenneth R. Brown
2009 Physical Review A. Atomic, Molecular, and Optical Physics  
This estimate is based on analyzing the impact of fault-tolerant quantum error correction in the context of the Quantum Logic Array (QLA) architecture.  ...  Comparison of our results to the resource requirements for a fault-tolerant implementation of Shor's quantum factoring algorithm reveals that the required logical qubit reliability is similar for both  ...  Additional details of the analysis of the architecture and the underlying logical qubit and operations design is provided in the appendix, including a detailed fault-tolerant threshold analysis for each  ... 
doi:10.1103/physreva.79.062314 fatcat:he2tgszdkzcivhxngh6hieo2wi

Roads towards fault-tolerant universal quantum computation

Earl T. Campbell, Barbara M. Terhal, Christophe Vuillot
2017 Nature  
A fault-tolerant computational procedure ensures that errors do not multiply and spread. This review compares the leading proposals for promoting a quantum memory to a quantum processor.  ...  We discuss the several no-go results which hold for low-dimensional topological codes and outline the potential rewards of using high-dimensional quantum (LDPC) codes in modular architectures.  ...  Clearly, any design of such a quantum computer will require a huge effort in integrated quantum circuit design and optimization, a quantum analog to VLSI design.  ... 
doi:10.1038/nature23460 pmid:28905902 fatcat:aqimnezcb5b4pd6ryptxgf7nqa

Subsystem Fault Tolerance with the Bacon-Shor Code

Panos Aliferis, Andrew W. Cross
2007 Physical Review Letters  
A 73, 012340 (2006)] leads to remarkably simple and efficient methods for fault-tolerant error correction (FTEC).  ...  By using these methods, we prove a lower bound on the quantum accuracy threshold, 1.94 × 10^-4 for adversarial stochastic noise, that improves previous lower bounds by nearly an order of magnitude.  ...  Universal quantum computation can be realized by including the logical phase gate, S expÿi 4 z , and one logical non-Clifford gate in our gate set; for a detailed discussion on achieving encoded quantum  ... 
doi:10.1103/physrevlett.98.220502 pmid:17677825 fatcat:jw7ny6ohvvd3haydctp24f4bxq

Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing [article]

Darshan D. Thaker , Isaac L. Chuang University of California at Davis, Massachusetts Institute of Technology)
2006 arXiv   pre-print
In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight.  ...  The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures.  ...  The ability to apply logical operations on a logical qubit without the need to decode and subsequently re-encode the data is key to the existence of fault-tolerant quantum microarchitecture design, where  ... 
arXiv:quant-ph/0604070v1 fatcat:pxi72hrcqvcvtoy74zuuwfjefq

Quantum Memory Hierarchies

Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong
2006 SIGARCH Computer Architecture News  
In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight.  ...  The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures.  ...  The ability to apply logical operations on a logical qubit without the need to decode and subsequently re-encode the data is key to the existence of fault-tolerant quantum microarchitecture design, where  ... 
doi:10.1145/1150019.1136518 fatcat:gduzbgycbvdxhaibph5g6ijrku
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