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A low-power and high-performance CMOS fingerprint sensing and encoding architecture
1999
IEEE Journal of Solid-State Circuits
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Index Terms-Cellular automaton, fingerprint encoding, fingerprint sensor, image processing, low-power design, neuron MOS, pixel-parallel circuits. ...
Image processing is achieved by application of hexagonal local operators implemented in pixel-parallel mixed neuron-MOS/CMOS logic circuits. ...
Jacobs for support in simulation techniques, H. Mulatz for packaging of the demonstrator chip, and C. Pacha for early conceptual discussions. ...
doi:10.1109/4.772413
fatcat:ydshea7ytrbvflg6p7n23u2q4q
3D design activities at Fermilab—Opportunities for physics
2010
Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment
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Fermilab began exploring the technologies for vertically integrated circuits (also commonly known as 3D circuits) in 2006. ...
These technologies include through silicon vias (TSV), circuit thinning, and bonding techniques to replace conventional bump bonds. ...
Acknowledgements The author wishes to thank the dedicated members of the ASIC group (G. Deptuch, J. Hoff, A. Shenai, M. Trimpl, and T. Zimmerman) who designed the circuits described in this paper. ...
doi:10.1016/j.nima.2009.09.045
fatcat:e6ddsyixh5b4dc5kdrscxscmsu
Amorphous IGZO Thin-Film Transistor Gate Driver in Array for Ultra-Narrow Border Displays
2022
IEEE Journal of the Electron Devices Society
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A gate driver in array (GIA) design based on the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is developed for narrow border displays. ...
Therefore, the pixel aperture ratio loss is minimized, and uniform placement of the gate driver circuits over the pixel array area is able to be achieved. ...
(a) Schematic of the gate driver circuit design being integrated within the pixel array area. (b) Timing diagram of the control signals. ...
doi:10.1109/jeds.2022.3164887
fatcat:i6wmsza7hnak5gzplg5mtkkuae
Image Processor and RISC MCU Embedded Single Chip Fingerprint Sensor
2020
Journal of Sensor and Actuator Networks
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The algorithm processor is a logic circuit that implements the GABOR filter and the THINNING step, which occupies 80% of the fingerprint image processing time. ...
The layout is done by automatic P&R for the full chip in a 96 × 96 pixel array. The chip area is 5010 μm × 5710 μm (28.61 mm2) and the gate count is 2,866,700. ...
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/jsan9040051
fatcat:u3iwacrpxzadllqt5xaqufqt6q
Design of Thin-Film-Transistor (TFT) arrays using current mirror circuits for Flat Panel Detectors (FPDs)
[article]
2011
arXiv
pre-print
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The TFTs arrays 4x4 matrix using current mirror circuits have been fabricated and tested with success. The TFTs array directly can process signals coming from 16 pixels in the same node. ...
This enables us to make the summation of the light intensities of close pixels during a reading. ...
The heart of the flat panel digital detector consists of a two-dimensional array of amorphous silicon photodiodes and thin-film transistors (TFTs) [1] , all deposited on a single substrate. ...
arXiv:1105.1407v1
fatcat:2qtsygguuvd2bj6scpcwo5d43e
CMOS-Integrated Si/SiGe Quantum-Well Infrared Microbolometer Focal Plane Arrays Manufactured With Very Large-Scale Heterogeneous 3-D Integration
2015
IEEE Journal of Selected Topics in Quantum Electronics
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The microbolometers are designed to detect light in the long wavelength infrared (LWIR) range from 8 to 14 μm and are arranged in focal plane arrays consisting of 384 × 288 microbolometer pixels with a ...
pixel pitch of 25 μm × 25 μm. ...
The focal plane array circuit contains an area for an array of 384 × 288 microbolometer pixels with a pixel pitch of 25 μm × 25 μm along with on-chip analog to digital conversion, compensation and communication ...
doi:10.1109/jstqe.2014.2358198
fatcat:acakogvmubhqpncbcyxbjid2qm
The heterogeneous integration of optical interconnections into integrated microsystems
2003
IEEE Journal of Selected Topics in Quantum Electronics
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onto a foundry Si CMOS microprocessor to demonstrate a single chip optically interconnected microprocessor, smart pixel emitter and detector arrays using resonant cavity enhanced P-i-N photodetectors ...
Demonstrations of interconnections using thin film heterogeneous integration technology include an integrated InGaAs/Si CMOS receiver circuit operating at 1 Gbps, an InGaAs thin film photodetector bonded ...
ACKNOWLEDGMENT The authors wish to thank the Microelectronics Research Center staff of the Georgia Institute of Technology, Atlanta, for their assistance with microfabrication, and DuPont for the donation ...
doi:10.1109/jstqe.2003.813307
fatcat:cklygy4rojbvvgfo5vbcerytza
A single-chip fingerprint sensor and identifier
1999
IEEE Journal of Solid-State Circuits
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The fingerprint identifier is formed by an array of pixels, and each pixel contains a sensing element and a processing element. ...
The sensing element senses capacitances formed by a finger surface to capture a fingerprint image. An identification is performed by the pixel-parallel processing of the pixels. ...
Wakimoto for their support and comments. ...
doi:10.1109/4.808910
fatcat:etazqkmtgreejcspahahtzzjem
Ultra-Thin Chips with ISFET Array for Continuous Monitoring of Body Fluids pH
2022
IEEE Transactions on Biomedical Circuits and Systems
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The SoUTC with the proposed current-mode active-pixel ISFET circuit array is desined to operate at 2V and consumes 6.28 W per-pixel. ...
This paper presents ISFET array based pH-sensing system-on-ultra-thin-chip (SoUTC) designed and fabricated in 350 nm CMOS technology. ...
Each IC of area 16 mm 2 consists of 512 ISFET pixel circuits distributed over the chip in a split-array format with a pitch of 40 µm between two adjacent individual pixel circuits of each array. ...
doi:10.1109/tbcas.2022.3141553
pmid:35007198
fatcat:nber5vn3obeo5ks3ru75al4t3y
Novel Method For The Analysis Of Printed Circuit Images
1984
Applications of Digital Image Processing VII
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These operations can be realized using simple processing elements which are well suited for implementation in hardware. * This is based on using a Vicom Model VDC 1600 with an array processor that can ...
A region is a set of nonzero pixels each of which is connected to all other pixels in the set. ...
Each algorithm uses a different thinning process designed so that a particular defect class induces a known corresponding class of skeletal features that can be easily and reliably detected. ...
doi:10.1117/12.944849
fatcat:joz46rwybjhbtai5i6up6pm3um
Trigger-wave collision detecting asynchronous cellular logic array for fast image skeletonization
2012
2012 IEEE International Symposium on Circuits and Systems
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This paper presents the design of an asynchronous cellular logic array for binary image processing algorithms based on wave propagation/collision in an excitable medium. ...
The proposed array could be used as a coprocessor in pixel-parallel SIMD architectures aiding the fast execution of medium-level image processing algorithms. ...
The proposed circuit will be of use in the design of pixel-parallel cellular processor array devices. Figure 1 . 1 Figure 1. ...
doi:10.1109/iscas.2012.6271852
dblp:conf/iscas/MroszczykD12
fatcat:zuyfj2wu2bdpjct7hx7xe7klzu
Novel method for analysis of printed circuit images
1985
IBM Journal of Research and Development
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These operations can be realized using simple processing elements which are well suited for implementation in hardware. * This is based on using a Vicom Model VDC 1600 with an array processor that can ...
A region is a set of nonzero pixels each of which is connected to all other pixels in the set. ...
Each algorithm uses a different thinning process designed so that a particular defect class induces a known corresponding class of skeletal features that can be easily and reliably detected. ...
doi:10.1147/rd.291.0073
fatcat:hxehdmbe2fecbdc42wbruaho7m
CMOS Active Pixel Sensor (APS) Imager for Scientific Applications
2002
Survey and Other Telescope Technologies and Discoveries
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This device is going to be used as a test vehicle to develop backside-thinning process. ...
A 512x512 CMOS Active Pixel Sensor (APS) imager has been designed, fabricate, and tested for frontside illumination suitable for use in astronomy specifically in telescope guider systems as a replacement ...
Work at the University of Arizona is supported by National Science Foundation Grant AST-9876630. ...
doi:10.1117/12.461429
fatcat:v37c2pmlonatdjtk4z3mcsb4uu
TMP5X5T1M: A Configurable Binary Morphological and Template Matching Processor
1996
IAPR International Workshop on Machine Vision Applications
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Ganesha 10 Bandung 40132 -I n d o n e s i a Phone. ...
The processor was fabricated in 0.8 pm CMOS Gate Array technology and has capability to process maximum 1024x 1024 pixels binary image with 5x5 template size in a speed of 200 ns per pixel at 10 MHz clock ...
Output mode consists of seven modes for single processing operations, nine modes for parallel processing operations, and one mode for parallel thinning operation. ...
dblp:conf/mva/YanuhardiAM96
fatcat:fw3qcrcfujha3kqrrf4nvwunuy
Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
2009
2009 IEEE International Conference on 3D System Integration
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A 1024 x 1024 diode array with 8-μm pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si. ...
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. ...
(a) Photo shows 3D vias in the array with Si readout circuit for each pixel. (b) Close up of the 3D via landing on PIN metal contact. ...
doi:10.1109/3dic.2009.5306556
dblp:conf/3dic/ChenYKCOMDSSBBHWKS09
fatcat:pydor6z6cja2bo6k26qlp66j5q
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