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Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
2007
19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07)
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In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). ...
Major contribution of this research is the design of an adaptive router architecture adopting a minimal adaptive routing algorithm with near optimal performance and feasible design complexity, satisfying ...
The performance and the total area overhead of the router demonstrated the feasibility of the on-chip interconnection network for a CMP realization. ...
doi:10.1109/sbac-pad.2007.38
fatcat:yfumtefarbd6rf575nbps22yry
Highly-scalable 3D CLOS NOC for many-core CMPs
2010
Proceedings of the 8th IEEE International NEWCAS Conference 2010
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In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and lowpower interconnect infrastructure ...
In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. ...
CONCLUSION This work shows the importance of high-radix NOCs for on-chip communication mechanisms in many-core CMPs and the suitability of CLOS networks with a reasonably high radix for interconnection ...
doi:10.1109/newcas.2010.5603776
fatcat:rbv2ofkjinav7onrwnr2ut2l2i
Revisiting accelerator-rich CMPs
2015
Proceedings of the 52nd Annual Design Automation Conference on - DAC '15
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Heterogeneous Chip MultiProcessors (CMP)s, which combine processor cores with specialized HW accelerators, are one main approach to high-performance low-power computing. ...
To illustrate the context, Fig. 1 outlines a typical ACC-based CMP, inspired by [4, 5] . The ACC-based CMP includes one or more processor cores loosely coupled with many ACCs. ...
INTRODUCTION The ever-increasing demand for high-performance low-power computing prompted the shift toward more specialization in Chip MultiProcessors (CMPs). ...
doi:10.1145/2744769.2744902
dblp:conf/dac/TeimouriTS15
fatcat:2dqrhh5ay5cvbn3e3gcoeq4p6y
A scalable micro wireless interconnect structure for CMPs
2009
Proceedings of the 15th annual international conference on Mobile computing and networking - MobiCom '09
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It makes the case for using a two-tier hybrid wireless/wired architecture to interconnect hundreds to thousands of cores in chip multiprocessors (CMPs), where current interconnect technologies face severe ...
We also devise new two-tier wormhole based routing algorithms that are deadlock free and ensure a minimum-latency route on a 1000core on-chip interconnect network. ...
Ministry of Defense under Agreement Number W911NF-06-3-0001. ...
doi:10.1145/1614320.1614345
dblp:conf/mobicom/LeeTPLCGRPNZC09
fatcat:fkelyqnjzndzxenh4uthc2dutu
StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs
2011
IEEE transactions on computers
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SN relies on a reconfigurable network of replicated processor pipeline stages to maximize the useful lifetime of a chip, gracefully degrading performance toward the end of life. ...
To this end, this paper presents and evaluates a highly reconfigurable CMP architecture, named as StageNet (SN), that is designed with reliability as its first-class design criteria. ...
., the US National Science Foundation grant CCF-0347411, and the Gigascale Systems Research Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research ...
doi:10.1109/tc.2010.205
fatcat:xs7oqbxxdnfb7nhze27oknj2jq
Adaptive and Speculative Slack Simulations of CMPs on CMPs
2010
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
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Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). ...
We show some simulation performance/accuracy data for a set of four Splash benchmarks in the context of an 8-core CMP with snooping protocol simulated on SlackSim, our versatile slack simulation platform ...
Introduction As computer architecture design rapidly moves into the chip multiprocessor (CMP) era, we cannot keep simulating CMPs in a sequential fashion as single processor systems are, because a single ...
doi:10.1109/micro.2010.47
dblp:conf/micro/ChenDWAD10
fatcat:kduexvxakvgxvabctfpncbq7yq
Efficient Hardware Barrier Synchronization in Many-Core CMPs
2012
IEEE Transactions on Parallel and Distributed Systems
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Through detailed simulations of a 32-core CMP, we compare GBarrier against one of the most efficient software-based barrier implementations for a set of kernels and scientific applications. ...
Our proposal deploys a dedicated G-line-based network to allow for fast and efficient signaling of barrier arrival and departure. ...
member of the Computer Engineering Department of the University of Murcia. ...
doi:10.1109/tpds.2011.304
fatcat:t2zl7yczyzastcl4r7vr2htic4
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
2008
IEEE computer architecture letters
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Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future chip multi-processor ( ...
BENoC (Bus-Enhanced Network on-Chip) possesses two main advantages: First, the bus is inherently capable of performing broadcast transmission in an efficient manner. ...
For example, multi-hop networks impose inherent multi-cycle packet propagation latency on the timesensitive communication between modules, making NoCs unattractive for CMP designers. ...
doi:10.1109/l-ca.2008.11
fatcat:nyjyva5wfrgypdvfmau62q5nui
A vertical bubble flow network using inductive-coupling for 3-D CMPs
2011
Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip - NOCS '11
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A wireless 3-D NoC architecture for CMPs, in which the number of processor and cache chips stacked in a package can be changed after the chip fabrication, is proposed by using the inductive coupling technology ...
We implemented a real 3-D chip that has onchip routers and inductive-coupling data transceivers using a 65nm process in order to show the feasibility of our proposal. ...
To sum up the network design for the wireless 3-D CMP, we summarize the rules each chip must comply as follows. • Network design rule 1: Each chip has a pair of data transceivers for uplink and downlink ...
doi:10.1145/1999946.1999955
dblp:conf/nocs/MatsutaniTSKONKKA11
fatcat:7ggegdvwqje6laae6bdpvq5jaa
StageWeb: Interweaving pipeline stages into a wearout and variation tolerant CMP fabric
2010
2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN)
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Our experiments show that through its wearout tolerance, a StageWeb chip performs up to 70% more cumulative work than a comparable chip multiprocessor. ...
Consequently, fault tolerance, historically of interest only for mission-critical systems, is now gaining attention in the mainstream computing space. ...
The authors acknowledge the support of the Gigascale Systems Research Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program. ...
doi:10.1109/dsn.2010.5544915
dblp:conf/dsn/GuptaAFM10
fatcat:fomccdvdxvgc5btcnwbunyhdba
A low-latency modular switch for CMP systems
2011
Microprocessors and microsystems
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Abstract As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. ...
Elsevier Roca Pérez, A.; Flich Cardo, J.; Silla Jiménez, F.; Duato Marín, JF. (2011). A low-latency modular switch for CMP systems. Microprocessors and Microsystems. 35(8):742-754. ...
Introduction and Motivation It is well-known that current Chip MultiProcessor (CMP) and high-end Mul-tiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. ...
doi:10.1016/j.micpro.2011.08.011
fatcat:6jwc76atr5fjzoazqt3dmmxlom
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
2007
2007 IEEE 13th International Symposium on High Performance Computer Architecture
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On the other hand, chip-multiprocessors (CMP) that integrate several processor cores in a single chip are nowadays the best alternative to more efficient use of the increasing number of transistors that ...
In this work, we present a coherence protocol aimed at dealing with transient failures that affect the interconnection network of a CMP, thus assuming that the network is no longer reliable. ...
Acknowledgements This work has been supported by the Spanish Ministry of Ciencia y Tecnología and the European Union (Feder Funds) under grant TIC2003-08154-C06-03. ...
doi:10.1109/hpca.2007.346194
dblp:conf/hpca/PascualGAD07
fatcat:wovatyfofrajdmp7fv464kcgoe
Achieving predictable performance through better memory controller placement in many-core CMPs
2009
Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09
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Limited pin bandwidth prevents the integration of a large number of memory controllers on-chip. ...
performance of memory-intensive applications regardless of the processing core on which a thread is scheduled. ...
Introduction Increasing levels of silicon integration are motivating system on chip (SoC) and chip multiprocessor (CMP) designs with large processor counts and integrated memory controllers. ...
doi:10.1145/1555754.1555810
dblp:conf/isca/AbtsJKGL09
fatcat:5mpmstkpkjcd3pyqupobqcnx3a
Achieving predictable performance through better memory controller placement in many-core CMPs
2009
SIGARCH Computer Architecture News
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Limited pin bandwidth prevents the integration of a large number of memory controllers on-chip. ...
performance of memory-intensive applications regardless of the processing core on which a thread is scheduled. ...
Introduction Increasing levels of silicon integration are motivating system on chip (SoC) and chip multiprocessor (CMP) designs with large processor counts and integrated memory controllers. ...
doi:10.1145/1555815.1555810
fatcat:zwagwcxsdnhd3mnks6f7vibaqe
Interleaving granularity on high bandwidth memory architecture for CMPs
2010
2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
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The increasing processor performance, and the advert of single chip multiprocessors have increased the memory bandwidth demands beyond what a single commodity memory device can provide. ...
Memory bandwidth has always been a critical factor for the performance of many data intensive applications. ...
ACKNOWLEDGMENT The authors want to thank Carlos Villavieja, Milan Pavlovic, Toni Quesada and Pieter Bellens for their contributions to the development of the simulator employed for this work. ...
doi:10.1109/icsamos.2010.5642060
dblp:conf/samos/CabarcasRER10
fatcat:jbufwbwqm5dexenl3feqhntjj4
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