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A Reconfigurable Computing Engine for Wavelet Transforms

Kang Sun, Xuezeng Pan, Lingdi Ping
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
In the past a few years, wavelet transforms have become a hot topic of research. Discrete and continuous wavelet transforms have been widely used in signal and multimedia processing.  ...  In order to validate this architecture, an FPGA prototype is built based on Xilinx VirtexII FPGA to test the reconfiguration of 2-D discrete 5/3 and 9/7 transforms (defined in specification of JPEG2000  ...  So it is significant to design a reconfigurable system by ASIC or reconfigurable hardware like FPGA for discrete and continuous wavelet transform of different wavelet filters.  ... 
doi:10.1109/ipdps.2007.370373 dblp:conf/ipps/SunPP07 fatcat:444qib7shndl7ar7tostu6funi

A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications

A. do Carmo Lucas, S. Heithecker, P. Ruffer, R. Ernst, H. Ruckert, G. Wischermann, K. Gebel, R. Fach, W. Huther, S. Eichner, G. Scheller
2006 Proceedings of the Design Automation & Test in Europe Conference  
It is based on Xilinx Virtex-II Pro FPGAs, large SDRAM memories for multiple frame storage and a PCI express communication network.  ...  performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth.  ...  Discrete Wavelet Transform The discrete wavelet transform (DWT) transforms a signal into a space where the base functions are wavelets [16] , similarly to the way Fourier transformation maps signals to  ... 
doi:10.1109/date.2006.244085 dblp:conf/date/LucasHRERWGFHES06 fatcat:hbbevsselngqditzhz4qqruuya

Design and FPGA Implementation of DWT, Image Text Extraction Technique

Adesh Kumar, Prakshi Rastogi, Pragyan Srivastava
2015 Procedia Computer Science  
The design is developed in Xilinx 14.2 ISE software and is synthesized on Virtex -5 FPGA.  ...  The paper focuses on the design, modeling and simulation of the proposed method with the help of VHDL programming language.  ...  are transformed to the wavelet domain using Haar wavelet.  ... 
doi:10.1016/j.procs.2015.07.512 fatcat:d3vlzd74cng57mxwxpsv3rabye

Algorithm development and hardware implementation for medical image compression system: a review

Noor Huda Ja'afar, Afandi Ahmad
2020 Indonesian Journal of Electrical Engineering and Computer Science  
The algorithm development using wavelet transform with software implementation are the famous topics explored among researchers, whilst fewer works have been done in utilizing curvelet transform in medical  ...  <br /> In conclusion, the overall picture of the medical image compression landscape, where most of the researchers more focused on algorithm development or software implementations without having the  ...  This paper is only concern on the transformation process based on Discrete Wavelet Transform (DWT) algorithm with aim to reduce the size of medical image and to speed up the processing of large medical  ... 
doi:10.11591/ijeecs.v18.i3.pp1331-1341 fatcat:irffewws7za45jw6e4ltipcqsq

An Optimized FPGA Based System Design for the Arrhythmia Detection using ECG

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
The framework based on FPGA is structured and executed in the paper which can detect a type of arrhythmia which indicates Atrio Ventricular block along with all the noises removed.  ...  FPGA prototyping of the design is carried out along the hardware debugging in chip scope pro tool. The design is realized using Verilog coding with the technique of morphological filtering.  ...  The objective of the study is to design and develop the arrhythmias detection system for ECG signaling using Haar wavelet transformation and morphological filtering based on FPGA.  ... 
doi:10.35940/ijitee.j9420.119119 fatcat:hbj4zy4iybd2rbmyhj4j2nc5vm

Image Denoising in FPGA using Generic Risk Estimation [article]

Rinson Varghese
2021 arXiv   pre-print
In this paper, we discuss an efficient FPGA implementation of this algorithm. We use the undecimated Haar wavelet transform with shrinkage parameters for each sub-band as the denoising function.  ...  We also show that the recursive implementation of Haar wavelet is more expensive than the direct implementation in terms of hardware utilization.  ...  GENRE BASED DENOISING USING UNDECIMATED WAVELET TRANSFORM In discrete wavelet transform (DWT), at every level of decomposition we down-sample the signal which removes redundant information.  ... 
arXiv:2111.08297v1 fatcat:2kvhbnwefzfbtnes4tku4jokre

A High-End Real-Time Digital Film Processing Reconfigurable Platform

Sven Heithecker, Amilcar do Carmo Lucas, Rolf Ernst
2007 EURASIP Journal on Embedded Systems  
As an example, a complex noise reduction algorithm including a 2.5-dimension discrete wavelet transformation (DWT) and a full 16 × 16 motion estimation (ME) at 24 fps, requiring a total of 203 Gops/s net  ...  The multiboard, multi-FPGA hardware/software architecture, is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large SDRAM memories for multiple frame  ...  Discrete wavelet transform The discrete wavelet transform (DWT) transforms a signal into a space where the base functions are wavelets [39] , similar to the way Fourier transformation maps signals to  ... 
doi:10.1186/1687-3963-2007-085318 fatcat:g2orfqgnkvcxpjxtf7hdujfafm

A High-End Real-Time Digital Film Processing Reconfigurable Platform

Sven Heithecker, Amilcar do Carmo Lucas, Rolf Ernst
2007 EURASIP Journal on Embedded Systems  
As an example, a complex noise reduction algorithm including a 2.5-dimension discrete wavelet transformation (DWT) and a full 16 × 16 motion estimation (ME) at 24 fps, requiring a total of 203 Gops/s net  ...  The multiboard, multi-FPGA hardware/software architecture, is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large SDRAM memories for multiple frame  ...  Discrete wavelet transform The discrete wavelet transform (DWT) transforms a signal into a space where the base functions are wavelets [39] , similar to the way Fourier transformation maps signals to  ... 
doi:10.1155/2007/85318 fatcat:pf7gyjxndjggfl6ug32ou4xqiy

Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

Naveed Mahmud, Esam El-Araby
2019 International Journal of Reconfigurable Computing  
More specifically, we propose using quantum wavelet transform (QWT) to reduce the dimensionality of high spatial resolution data.  ...  The quantum wavelet transform takes advantage of the principles of quantum mechanics to achieve reductions in computation time while processing exponentially larger amount of information.  ...  Christopher Rogan from the department of Physics and Astronomy at the University of Kansas for their valuable insights and help in this work.  ... 
doi:10.1155/2019/1949121 fatcat:qnx7hfieajdsrf2wvxnp4t2euu

Design of an Efficient Steganography Model using Lifting based DWT and Modified-LSB Method on FPGA

Mahesh A A, Raja K.B
2019 International Journal of Advanced Computer Science and Applications  
In this research work, Design of an Efficient Steganography Model using Lifting Based DWT and Modified-LSB Method on FPGA is proposed.  ...  The steganography model is designed using Verilog-HDL on Xilinx platform and implemented with Artix-7 Field Programmable Gate Array (FPGA).  ...  Usage of inappropriate spatial or transformation domain usage, which causes computation complexity and leads to low-quality image outcomes.  ... 
doi:10.14569/ijacsa.2019.0101032 fatcat:kcaj47e3oneybbnpyzzgqpr3bm

VLSI Implementation of Image Fusion Using DWT- PCA Algorithm with Maximum Selection Rule

Surya Borra, Prasad V. Potluri Siddhartha Institute of Technology, Rajesh Panakala, Pullakura Kumar, Prasad V. Potluri Siddhartha Institute of Technology, Andhra University
2019 International Journal of Intelligent Engineering and Systems  
This work is implemented in FPGA. The combination of Discrete Wavelet Transform (DWT) and Principle Component Analysis (PCA) is known as hybrid algorithm.  ...  To improve the low dose CT scan, Hybrid algorithm is introduced in this paper which is implemented in FPGA. The main objective of this work is to optimize performances of the hardware.  ...  In the future, different kind of optimization algorithm will be designed to improve the ASIC and FPGA performances. 1 . 1 Figure.1 Block diagram of entire process Figure. 2 2 Figure.2 Discrete wavelet  ... 
doi:10.22266/ijies2019.1031.01 fatcat:hvzmibarqrca5k4xehrv6qrfvm

A comparative analysis of 1-level multiplier-free discrete wavelet transform implementations on FPGAs

Husam ALZAQ, Burak Berk ÜSTÜNDAĞ
2018 Turkish Journal of Electrical Engineering and Computer Sciences  
In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform  ...  The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6's embedded block RAMs.  ...  Background Discrete wavelet transform The wavelet decomposition mainly depends on the orthonormal filter banks.  ... 
doi:10.3906/elk-1707-101 fatcat:3eaumfvbubcldg3pbbtkywjm3y

Implementation Of Encryption And Watermarking Algorithm For Remote Sensing Image

Faruk Ahmed
2016 International Journal Of Engineering And Computer Science  
Wavelet Transform for remote sensing image  ...  This paper presents the processing of remote sensing image using water marking and encryption algorithm.  ...  Performing DWT transform of the watermark image In numerical analysis and functional analysis, a discrete wavelet transform (dwt) is any wavelet transform for which the wavelets are discretely sampled.  ... 
doi:10.18535/ijecs/v5i8.36 fatcat:qvrwm7l66jdd7fnsggh7l7mehq

Reconfigurable architecture for real-time image compression on-board satellites

Kristian Manthey, David Krutz, Ben Juurlink
2015 Journal of Applied Remote Sensing  
The requirements, the design of the architecture, and its implementation based on reconfigurable hardware are presented.  ...  A Xilinx Virtex-5QV enables thereby compressing images with a width of up to 4096 pixels without the use of external memory.  ...  The HRSST is a joint program of Technische Universität Berlin (TUB) and DLR.  ... 
doi:10.1117/1.jrs.9.097497 fatcat:32vnqdyok5dzxp2vv5oocpmwjq

Very-low-SNR cognitive receiver based on wavelet preprocessed signal patterns and neural network

Husam Y. Alzaq, B. Berk Ustundag
2017 EURASIP Journal on Wireless Communications and Networking  
However, efficient spectral bandwidth usage under the influence of higher noise is not the major consideration of CR.  ...  The cognitive receiver preprocesses the received signal by extracting a limited set of wavelet features.  ...  Acknowledgements The authors would like to thank the anonymous reviewers for their valuable comments and suggestions to improve the quality of the article.  ... 
doi:10.1186/s13638-017-0902-7 fatcat:yvtl6yd3obcv3pse6n6y7edv74
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