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A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS
2008
2008 IEEE Asian Solid-State Circuits Conference
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Maximum thermal design power (TDP) consumption is measured at 2 W at 1.0 V, 90 C using a synthetic power-virus test at a frequency of 1.86 GHz. ...
The design contains 47 million transistors in a die size under 25 mm manufactured in a 9-metal 45 nm CMOS process with optimized transistors for low leakage. ...
Nguyen, Giridhar Vadlamudi and Chris Weaver for data collection. ...
doi:10.1109/asscc.2008.4708718
fatcat:s75igiqee5elva2crdciwgk2zi
Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing
2018
IEICE transactions on electronics
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CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. ...
On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. ...
Acknowledgments This work was supported in a part by JSPS KAKENHI Grant Number JP16H02796. ...
doi:10.1587/transele.e101.c.359
fatcat:ifndzli3cvbybhwlvqwraa3fhq
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
2008
IEEE Journal of Solid-State Circuits
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The fully functional first silicon achieves over 1.0 TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07 V supply. ...
In a 65-nm eight-metal CMOS process, the 275 mm 2 custom design contains 100 M transistors. ...
Frumkin from SSG and ARL teams at Intel for assistance with mapping the kernels to the design; the LTD and ATD teams for PLL and package design and assembly; the entire mask design team for chip layout ...
doi:10.1109/jssc.2007.910957
fatcat:nilal7bs7rh77hjna5u2evdjhi
Large chip vs. MCM for a high-performance system
1998
IEEE Micro
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To effect this test methodology, designers should place boundary-scan latches on the module I/O (system I/O) only, and the entire function should be tested as if it were a single-chip microprocessor for ...
Microprocessor designers know what they must do to reach a 1-GHz clock rate. Beyond this point, however, the path is not so obvious. ...
AI, spacecraft engineering, mission design, software engineering, and system engineering all have a role to play in these developments. ...
doi:10.1109/40.710869
fatcat:oob575l26fc53docqc2dreqhk4
Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors
2006
IEEE Transactions on Nuclear Science
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The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. ...
Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. ...
in the GHz range. ...
doi:10.1109/tns.2006.884383
fatcat:vvjxrdgxjjb5rblme5dafs2ece
VCO Design using NAND Gate for Low Power Application
2016
JSTS Journal of Semiconductor Technology and Science
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Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. ...
Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. ...
The proposed VCOs achieves the output frequency from 3.318 GHz to 5.604 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages design for the coarse tuning mode ...
doi:10.5573/jsts.2016.16.5.650
fatcat:deatzoo5vvgy3awqz2s45qinxe
A 1.0-GHz single-issue 64-bit powerPC integer processor
1998
IEEE Journal of Solid-State Circuits
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The organization and circuit design of a 1.0-GHz integer processor built in 0.25-m CMOS technology are presented. ...
A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented. ...
Stawiasz for their expertise and dedication in testing the hardware. ...
doi:10.1109/4.726542
fatcat:kjy4gwd3wndspkhjsvewazmcmq
Interconnect opportunities for gigascale integration
2002
IBM Journal of Research and Development
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Using a heterogeneous version of Rent's rule, a design methodology for the global signal, clock, and power/ground distribution networks for a system-on-a-chip has been derived. ...
Wiring area, bandwidth, and signal integrity are the prime constraints on the design of the networks. ...
MDA 972-99-1-002, and the SRC, Contract No. 448:048, for their generous support. ...
doi:10.1147/rd.462.0245
fatcat:rne5dmy6tjbjfe6d5dgkimswxm
An analysis of ADPLL applications in various fields
2020
Indonesian Journal of Electrical Engineering and Computer Science
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The design gives a frequency range from 1.0-5.5GHz with low power consumption and it can also be used for Clock generation applications. </span> ...
ADPLL consists of a phase detector, loop filter and digital controlled oscillator. ...
The ADPLL is designed with separate locking scheme for frequency and phase. ADPLL for microprocessor applications need high-volume, high-performance with low-power. ...
doi:10.11591/ijeecs.v18.i2.pp856-866
fatcat:f5syzddqhvchtiercom5f37sb4
Distributed Differential Oscillators for Global Clock Networks
2006
IEEE Journal of Solid-State Circuits
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The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. ...
Measurement results from a prototype design implemented in a 0.18-m CMOS technology show almost an order of magnitude less jitter and power than a traditional treedriven grid global clock distribution. ...
Manager in the VLSI Design Department at the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he was responsible for the design methodology for IBM's G4 S/390 microprocessors. ...
doi:10.1109/jssc.2006.880610
fatcat:tl42xraavndyzkia2pvqi7fcgu
A simple methodology for on-chip transmission line modeling and optimization for high-speed clock distribution
2019
Japanese Journal of Applied Physics
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With the recent increases in data bandwidth, frequency and chip area in VLSI systems, the design methodology for on-chip clock distribution lines has been changing from an RC-model to an RLC-model and ...
We applied our proposed methodology to a 9 mm on-chip clock distribution line with various metal layer combinations at 3 GHz in the TSMC 0.18 μm 1-poly 6-metal CMOS fabrication process. ...
The authors would like to thank Masayuki Katakura from Sony LSI Design Inc. for his valuable comments. ...
doi:10.7567/1347-4065/ab02e0
fatcat:y3qe5a3osrhgdlx5oatjw4dx2u
COMPACT MICROSTRIP UWB BANDPASS FILTER WITH TRIPLE-NOTCHED BANDS
2013
Progress In Electromagnetics Research C
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For verification, a microstrip UWB BPF with triple-notched bands respectively centered at frequencies of 4.3 GHz, 5.8 GHz, and 8.1 GHz is designed and fabricated. ...
The triple-notched bands can be easily generated and set at any desired frequencies by varying the designed parameters of SRSSLR. ...
The study is completed on a computer with a 2-GHz microprocessor, and the computing time of the example is only 1.8 min. ...
doi:10.2528/pierc13053103
fatcat:cffnb23f3vga3nxt24doxgbriq
Silicon carrier for computer systems
2006
Proceedings of the 43rd annual conference on Design automation - DAC '06
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System-on-Package (SOP) based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies for a wide range of two-and ...
The paper also discusses some methodologies that may allow silicon carrier technical elements to be easily integrated within existing EDA tools. ...
For example, consider a case where signal A is operating at 10 GHz and a wiring pitch of 50 μm and signal B is operating at 2 GHz and wiring pitch of 4 μm.
Figure 7a . 7a Figure 7a. ...
doi:10.1145/1146909.1147128
dblp:conf/dac/Patel06
fatcat:m65xub5t65hslmo6agphjpjoui
Silicon carrier for computer systems
2006
Proceedings - Design Automation Conference
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System-on-Package (SOP) based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies for a wide range of two-and ...
The paper also discusses some methodologies that may allow silicon carrier technical elements to be easily integrated within existing EDA tools. ...
For example, consider a case where signal A is operating at 10 GHz and a wiring pitch of 50 μm and signal B is operating at 2 GHz and wiring pitch of 4 μm.
Figure 7a . 7a Figure 7a. ...
doi:10.1109/dac.2006.229241
fatcat:qesxlmuqzveateo6lyuhuwc6gu
Clock power minimization using structured latch templates and decision tree induction
2013
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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The proposed methodology first generates optimized placement solutions for a wide range of input configurations. ...
Additionally, because of a priori generation, template selection during physical design is extremely fast. ...
Because of this, latch clustering has become the de facto methodology for multi-Ghz designs. Figure 2 shows snapshot of a multi-Ghz design employing the conventional clustering approach. ...
doi:10.1109/iccad.2013.6691178
dblp:conf/iccad/WardVZSLAP13
fatcat:vrkpwhtbxverbg3v4wtyynppze
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