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Reduction of Test Time using Multiple Test Control Point Insertion for 7nm Technology Node

2020 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
Test time reduction is a prominent challenge in scan based Design For Testability (DFT) architectures for cost effective test.  ...  Reliability and testability both are main objectives for DFT in today's VLSI design. In this paper, we have proposed multiple standard test control point insertion technique for 7nm technology node.  ...  Tests based on scan architecture is the most predominantly used solution in order to achieve high fault coverage, the test doesn't consider the problems of large volume of test data which is recognized  ... 
doi:10.35940/ijitee.e2946.039520 fatcat:274lvhd3yff25fddjy4opgwnza

Comments on "Filling algorithms and analyses for layout density control"

Rung-Bin Lin
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Unfortunately, performing test modifications after the SOC design has been optimized for target design constraints does not preserve the optimality of the solution obtained.  ...  Embedded systems are increasingly synthesized today as systems-on-a-chip (SOCs), wherein existing functional blocks (also called cores) are used to implement different functions in the system specification  ...  ACKNOWLEDGMENT The authors would like to thank the Associate Editor and the anonymous reviewers for their helpful comments and suggestions.  ... 
doi:10.1109/tcad.2002.802262 fatcat:lif5d7bimjbezieckvo2t3b5uu

Efficient Test Solutions for Core-Based Designs

E. Larsson, K. Arvidsson, H. Fujiwara, Z. Peng
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test.  ...  A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed  ...  In the distributed architecture, the testing of all cores are started at the same time, which means that all cores are activated simultaneously, resulting in a high test-power consumption.  ... 
doi:10.1109/tcad.2004.826560 fatcat:3qvtygpxrjf7tpu3j64enumjly

Environment for the analysis of functional self-test quality in digital systems

R Ubar, S Kostin, H Kruus, M Aarna, S Devadze
2014 Proceedings of the Estonian Academy of Sciences  
We propose a new methodology for Built-in Self-Test (BIST), which combines the inherent functionality of the architecture with a small amount of pre-generated test data stored in the memory, and uses for  ...  One of the possibilities to increase the dependability is to develop architectures with dedicated self-test capabilities which allow achieving high quality of testing in terms of fault coverage.  ...  the Estonian Ministry of Education and Research, and ESF grants 8478 and 9429.  ... 
doi:10.3176/proc.2014.2.05 fatcat:23gjasdwovejfbh7j5hi2bw4be

Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

Wei Hwang, G. Gristede, P. Sanda, S.Y. Wang, D.F. Heidel
1999 IEEE Journal of Solid-State Circuits  
The adder core is composed of evaluate circuits and feedback reset chains implemented by selfresetting CMOS (SRCMOS) circuits with enhanced testability.  ...  A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance.  ...  Nguyen for their first-version adder design and contributions; V. Narayanan, S. Basavaiah, B. Fleischer, P. Cook, P. Emma, and L. Terman for their helpful discussions and comments; and J.  ... 
doi:10.1109/4.777109 fatcat:tn2umlmhpfghph545hrtv5ttfi

Object-oriented reuse methodology for VHDL

Cristina Barna, Wolfgang Rosenstiel
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
In contrast to conventional reuse approaches, which imply a considerable re-design effort, this new approach bridges the gap between design and reuse integration.  ...  The methodology is implemented in the form of a Reuse Management System which handles the classification, modification, adaption, storage and retrieval of the reuse components.  ...  Most of the researchers also propose complete systems for integrating the IP components in designs and focus on verification and validation at a very high level of abstraction [6] .  ... 
doi:10.1145/307418.307590 fatcat:rjtuyync7nfnlf5jta736xxivq

Power-/energy-efficient BIST schemes for processor data paths

N. Kranitis, D. Gizopoulos, A. Paschalis, M. Psarakis, Y. Zorian
2000 IEEE Design & Test of Computers  
is primarily consumed in a data path consisting of high-activity functional modules.  ...  In contemporary SOC designs many intellectual property (IP) cores are tested in parallel within the same BIST session, Power-/Energy-Efficient BIST Schemes for Processor Data Paths Processor core power  ...  9 Special care is taken for the low-power design of the vector-masking control logic that may result in high area overhead.  ... 
doi:10.1109/54.895003 fatcat:yjsjfrzdvjclvdggh47dwih43a

Energy Efficient and Fault Tolerant Multicore Wireless Sensor Network: E²MWSN

Hong-Ling Shi, Kun Mean Hou, Hai-Ying Zhou, Xing Liu
2011 2011 7th International Conference on Wireless Communications, Networking and Mobile Computing  
High Reliability Design Process dedicated to Resource Constraint Embedded System 75 whole develop process following the Design-For-Testability Way.  ...  Because the test and validation process in multicore WSN node is carried out in real-time, so we name this method as Design for Multicore Run Time Testability (DMRTT).  ...  FSMOS High-level Architecture The high-level architecture of FSMOS is presented on the Figure 7-6.  ... 
doi:10.1109/wicom.2011.6040317 fatcat:b6qehpnmxjd35go7ycy5v5ru5y

Software-based delay fault testing of processor cores

Singh, Inoue, Saluja, Fujiwara
2003 Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03  
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in functional mode using its instruction  ...  A systematic approach for the generation of test vectors, which are applicable in functional mode, is presented.  ...  Acknowledgement This work was supported in part by Semiconductor Technology Academic Research Center (STARC) under the research project.  ... 
doi:10.1109/ats.2003.1250785 dblp:conf/ats/SinghISF03 fatcat:oak6pj2nqvgzhjoj22m3lnludu

Optimized Test compression bandwidth management for Ultra-large-Scale System-on-Chip Architectures performing Scan Test Bandwidth Management

Vengala Abhilash
2016 International Journal Of Engineering And Computer Science  
As the core count increases, the need for a scalable on-chip communication fabric that can deliver high bandwidth is gaining in importance, leading to recent multicore chips interconnected with sophisticated  ...  With Moore's law supplying billions of transistors, and uni-processor architectures delivering diminishing performance, multicore chips are emerging as the prevailing architecture in both generalpurpose  ...  Contemporary circuit growth in size forced division of design project into independent functional parts.  ... 
doi:10.18535/ijecs/v5i10.36 fatcat:ds2yquorzzembhf2hbfmfbzwz4

A concurrent testing method for NoC switches

M. Hosseinabady, A. Banaiyan, M.N. Bojnordi, Z. Navabi
2006 Proceedings of the Design Automation & Test in Europe Conference  
This paper proposes reuse of on-chip networks for testing switches in Network on Chips (NoCs).  ...  This algorithm alleviates the need for: (1) external comparison of the output response of the circuit-under-test with the response of a fault free circuit stored on a tester (2) on-chip signature analysis  ...  Since the NoCs consist of functional cores, switch cores and interfaces, test methodologies should be performed on each of these three parts.  ... 
doi:10.1109/date.2006.244018 dblp:conf/date/HosseinabadyBBN06 fatcat:ci7gajdffvb7zdwwazfz6q6ove

Multilevel Full-Chip Routing With Testability and Yield Enhancement

Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening  ...  We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement.  ...  For example, the ORT architecture in Fig. 2 consists of one OR and a neighboring net, and two scan paths in cores C 1 and C 2 are part of the OR.  ... 
doi:10.1109/tcad.2007.895587 fatcat:t4des4udfjgxfnvb7kcumnktei

How Europe Is Preparing Its Core Solution for Exascale Machines and a Global, Sovereign, Advanced Computing Platform

Mario Kovač, Philippe Notton, Daniel Hofman, Josip Knezović
2020 Mathematical and Computational Applications  
One of EPI's core activities also takes place in the automotive sector, providing architectural solutions for a novel embedded high-performance computing (eHPC) platform and ensuring the overall economic  ...  In this paper, we present an overview of the European Processor Initiative (EPI), one of the cornerstones of the EuroHPC Joint Undertaking, a new European Union strategic entity focused on pooling the  ...  It is a design adaptive standard cell-based architecture that provides the highest degree of design customization, best-in-class testability and fastest time-to-volume for SoC design, targeting any production  ... 
doi:10.3390/mca25030046 fatcat:vsnp2imx4bf3pj3lgk2e7qoz3e

Multilevel full-chip routing with testability and yield enhancement

Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu-E Chen
2005 Proceedings of the 2005 international workshop on System level interconnect prediction - SLIP '05  
We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening  ...  We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement.  ...  For example, the ORT architecture in Fig. 2 consists of one OR and a neighboring net, and two scan paths in cores C 1 and C 2 are part of the OR.  ... 
doi:10.1145/1053355.1053362 dblp:conf/slip/LiLCSC05 fatcat:rtkimxs7ingppmv7xq6hqakjlu

Low Cost Built in Self Test for Public Key Crypto Cores

Duško Karaklajic, Miroslav Kneževic, Ingrid Verbauwhede
2010 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography  
The testability of the cryptographic cores brings in an extra dimension to the process of digital circuits testing -security.  ...  Furthermore, the multiplier becomes a fully self-testable design. All the additional features come at the cost of only a few extra gates.  ...  Testability is considered during design and needs to be addressed with the design of the rest of the system.  ... 
doi:10.1109/fdtc.2010.12 dblp:conf/fdtc/KaraklajicKV10 fatcat:wejcjt5krja45c77bfoypnsom4
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