Filters








2,248 Hits in 4.9 sec

Hybrid cache architecture with disparate memory technologies

Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ram Rajamony, Yuan Xie
2009 SIGARCH Computer Architecture News  
We discuss and evaluate two types of hybrid cache architectures: inter cache Level HCA (LHCA), in which the levels in a cache hierarchy can be made of disparate memory technologies; and intra cache level  ...  In this paper, we propose to take advantage of the best characteristics that each technology offers, through the use of Hybrid Cache Architecture (HCA) designs.  ...  In our RHCA design, the latency as well as power differences are from disparate memory technologies. Additionally, our RHCA is a hierarchical design.  ... 
doi:10.1145/1555815.1555761 fatcat:7ccicagzabfevbrdmht65mytce

Hybrid cache architecture with disparate memory technologies

Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ram Rajamony, Yuan Xie
2009 Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09  
We discuss and evaluate two types of hybrid cache architectures: inter cache Level HCA (LHCA), in which the levels in a cache hierarchy can be made of disparate memory technologies; and intra cache level  ...  In this paper, we propose to take advantage of the best characteristics that each technology offers, through the use of Hybrid Cache Architecture (HCA) designs.  ...  In our RHCA design, the latency as well as power differences are from disparate memory technologies. Additionally, our RHCA is a hierarchical design.  ... 
doi:10.1145/1555754.1555761 dblp:conf/isca/WuLZSRX09 fatcat:mf2waz6yonhwzbb673bm25op2m

Power and performance of read-write aware Hybrid Caches with non-volatile memories

Xiaoxia Wu, Jian Li, Lixin Zhang, E. Speight, Yuan Xie
2009 2009 Design, Automation & Test in Europe Conference & Exhibition  
of cache can be partitioned into read and write regions, each of a different memory technology with disparate read and write characteristics.  ...  In this paper, we propose to take advantage of the best characteristics that each technology has to offer through the use of read-write aware Hybrid Cache Architecture (RWHCA) designs, where a single level  ...  In our RWHCA design, the latency as well as power differences are from disparate memory technologies. Additionally, our RWHCA is a hierarchical design.  ... 
doi:10.1109/date.2009.5090762 dblp:conf/date/WuLZSX09 fatcat:zmwzb4kewvgivcmmdb5qtwjfgy

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design

Yu-Ting Chen, J. Cong, Hui Huang, Bin Liu, Chunyue Liu, M. Potkonjak, G. Reinman
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
The recent development of non-volatile memory (NVM), such as spin-torque transfer magnetoresistive RAM (STT-RAM) and phase-change RAM (PRAM), with the advantage of low leakage and high density, provides  ...  We propose a novel reconfigurable hybrid cache architecture (RHC), in which NVM is incorporated in the last-level cache together with SRAM.  ...  In RHC different memory technologies (SRAM and NVM) are unified at the same cache level to form a hybrid design, and power gating circuitry is introduced to allow adaptive powering on/off of SRAM/NVM sub-arrays  ... 
doi:10.1109/date.2012.6176431 dblp:conf/date/ChenCHLLPR12 fatcat:eugxbqfikjdaxprrzc5lw3oobu

Design Guidelines for High-Performance SCM Hierarchies [article]

Dmitrii Ustiugov, Alexandros Daglis, Javier Picorel, Mark Sutherland, Edouard Bugnion, Babak Falsafi, Dionisios Pnevmatikatos
2018 arXiv   pre-print
We identify the set of memory hierarchy design parameters that plays a key role in the performance and cost of a memory system combining an SCM technology and a 3D stacked DRAM cache.  ...  and the mitigation of SCM's read/write latency disparity.  ...  To guide system designers through this complex design space, we devise a design exploration methodology for different SCM technologies.  ... 
arXiv:1801.06726v3 fatcat:f35hkiudqfbrdll2lhoe3hfime

Memory system design space exploration for low-power, real-time speech recognition

Rajeev Krishna, Scott Mahlke, Todd Austin
2004 Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04  
This work presents a design space exploration of potential memory system architectures.  ...  DRAM and ROM technologies can provide much of the performance of idealized memory systems without violating the power constraints of the low-power domain.  ...  MEMORY SYSTEM COMPONENTS We now begin a consideration of off-chip components of L2 cache with SDRAM memory over those with DDR memory and no L2 cache. the memory system.  ... 
doi:10.1145/1016720.1016756 dblp:conf/codes/KrishnaMA04 fatcat:n6hy6j7hb5e4rjrfztoogwxiha

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches

Sparsh Mittal, Jeffrey S. Vetter, Dong Li
2015 IEEE Transactions on Parallel and Distributed Systems  
In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies.  ...  To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory  ...  Several hybrid cache designs use this approach to architect different cache ways using disparate memory technologies (e.g. [41, 43, 103] ).  ... 
doi:10.1109/tpds.2014.2324563 fatcat:siuvjd3syjad5kfqkpy2mhojny

New Memory Organizations for 3D DRAM and PCMs [chapter]

Ademola Fawibe, Jared Sherman, Krishna Kavi, Mike Ignatowski, David Mayhew
2012 Lecture Notes in Computer Science  
Multi and many core systems are placing severe demands on caches, exacerbating the performance disparity between memory and processors.  ...  The memory wall (the gap between processing and storage speeds) remains a concern to computer systems designers.  ...  We explored a number of design parameters with our CMM design including page sizes, subpage sizes, prefetching additional subpages, use of victim CMM and associativites.  ... 
doi:10.1007/978-3-642-28293-5_17 fatcat:673dhiv23nfevbtm4iov2gouna

Prefetching in Hybrid Main Memory Systems

Subisha V, Varun Gohil, Nisarg Ujjainkar, Manu Awasthi
2020 USENIX Workshop on Hot Topics in Storage and File Systems  
Design of such hybrid architectures remains an active area of research from the perspective of DRAM-as-a-cache design, since DRAM could quickly become the bottleneck, as cache lookups require multiple  ...  This transformation is being carried out by either splitting the memory address across two or more memory technologies, or using a faster technology with higher lifetimes, typically the DRAM, as a cache  ...  From design space exploration, we find that it is best to have a 4 way set associative table with 1024 sets for the PRT. This table is 20KBs, with a single entry of 5 bytes.  ... 
dblp:conf/hotstorage/VGUA20 fatcat:v6en5urm25am5av47ycoqfkbnq

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Sparsh Mittal, Rujia Wang, Jeffrey Vetter
2017 Journal of Low Power Electronics and Applications  
technologies together, SRAM-NVM hybrid caches and DRAM-NVM hybrid main memory can be designed.  ...  hybrid memory designs [4, 5] .  ... 
doi:10.3390/jlpea7030023 fatcat:bfcgdptx5vflndypvec5vzg2ye

An energy efficient cache design using spin torque transfer (STT) RAM

Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili
2010 Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design - ISLPED '10  
This work explores the use of a novel non-volatile memory technology -"Spin Torque Transfer RAM (STT RAM)" for the design of the L2/LLC caches.  ...  This also makes STTRAM compatible with the SRAM process. Consequently hybrid designs are possible.  ... 
doi:10.1145/1840845.1840931 dblp:conf/islped/RasquinhaCCMY10 fatcat:ztl4urw57jc5bannudakp5qk3m

Statistical Behavior Guided Block Allocation in Hybrid Cache based Edge Computing for Cyber-Physical-Social Systems

Fanfan Shen, Chao Xu, Jun Zhang
2020 IEEE Access  
INDEX TERMS Statistical behavior, block allocation, non-volatile memory, hybrid cache.  ...  Hybrid cache consisting of spin-transfer torque RAM (STT-RAM) and static RAM (SRAM) has been proposed as last level cache (LLC) for energy efficiency recently in CPSS.  ...  [12] proposed inter cache level and intra cache level hybrid cache architecture with disparate memory technologies. Zhao et al. [13] proposed a bandwidth-aware reconfigurable hybrid cache.  ... 
doi:10.1109/access.2020.2972305 fatcat:i3kghhzwmrcjlblq3ibsfq2fn4

Preface

Xian-He Sun, Dong Li, Wen-Guang Chen, Tao Li, Ji-Wu Shu, Bo Wu, Jin Xiong, Jinging Xue, Feng Zhang, Ji-Dong Zhai, Zhiia Zhao
2021 Journal of Computer Science and Technology  
His research interests include data-intensive high-performance computing, memory and I/O systems, software system for big data applications, and performance evaluation and optimization.  ...  He is the Associate Chief Editor of IEEE Transactions on Parallel and Distributed Systems, a Golden Core member of the IEEE CS Society, and the past chair of the Computer Science Department at IIT.  ...  Several memory technologies and architectures including 3Dstacked memory, non-volatile random-access memory (NVRAM), memristor, hybrid software and hardware caches, etc. have been introduced in recent  ... 
doi:10.1007/s11390-021-0001-4 fatcat:f6kzf7226jbltpygejrg5wwut4

On Automated Feedback-Driven Data Placement in Multi-tiered Memory [chapter]

T. Chad Effler, Adam P. Howard, Tong Zhou, Michael R. Jantz, Kshitij A. Doshi, Prasad A. Kulkarni
2018 Lecture Notes in Computer Science  
This work explores a variety of cross-layer strategies for managing application data in multitiered memory.  ...  Recent emergence of systems with multiple performance and capacity tiers of memory invites a fresh consideration of strategies for optimal placement of data into the various tiers.  ...  (HBM, WIO2) memories, as well as a number of other academic and emerging memory technologies.  ... 
doi:10.1007/978-3-319-77610-1_14 fatcat:5dzbei2zuvemtnk36vjtenqsuq

Godson-T: An Efficient Many-Core Processor Exploring Thread-Level Parallelism

Dongrui Fan, Hao Zhang, Da Wang, Xiaochun Ye, Fenglong Song, Guojie Li, Ninghui Sun
2012 IEEE Micro  
Acknowledgments Godson-T represents the combined efforts of many diligent ICT researchers, engineers, and students across multiple teams in the State Key Laboratory of Computer Architecture of China.  ...  The data cache can also be configured as scratch-pad memory (SPM) or a hybrid structure of SPM and a data cache. The second level is the global L2 cache shared by all the cores.  ...  Four L2 cache banks on the same side of the chip share a memory controller (see Figure 1 ). Each L2 cache bank is connected with a router.  ... 
doi:10.1109/mm.2012.32 fatcat:ki3ygpfmlfd45j6sobh2jvxbfy
« Previous Showing results 1 — 15 out of 2,248 results