The Internet Archive has digitized a microfilm copy of this work. It may be possible to borrow a copy for reading.
Allen 831:68048 Design and synthesis of synchronization skeletons using branching time temporal logic. Logics of programs (Yorktown Heights, N.Y., 1981), pp. 52-71, Lecture Notes in Comput. ... From the introduction: “We propose a method of constructing concurrent programs in which the synchronization skeleton of the program is automatically synthesized from a high-level (branching time) temporal ...
The framework also supports synthesis of synchronization at different levels of abstraction and granularity. ... The specification language is an extension of propositional Computation Tree Logic (CTL) that enables easy specification of safety and liveness properties over control and data variables. ... Acknowledgements: The author wishes to thank Jyotirmoy Deshmukh for many insightful discussions during the course of writing this paper, and an anonymous reviewer for pointing out interesting future research ...doi:10.4204/eptcs.84.2 fatcat:ny57q2e7lncihlbw7t7nkzny4a
Allen Emerson, Design and synthesis of synchronization skeletons using branching time temporal logic (pp. 52-71); Robert L. Constable and Daniel R. Zlatin, The type theory of PL/CV3 (pp. 72-93); J. ... of concurrent programs: temporal proof principles (pp. 200-252); Zohar Manna and Pierre Wolper, Synthesis of communicating processes from temporal logic specifications (pp. 253-281); Albert R. ...
In this paper we present a framework and associated techniques to generate the process model of a service composition from a set of temporal business rules. ... Dedicated techniques including pathfinding, branching structure identification and parallel structure identification are used for semi-automatically synthesizing the process model from the semantics-equivalent ... For example, Beeck et al. use Semantic Linear-Time Temporal Logic to synthesis state charts  . Uchitel et al. use Message Sequence Charts to synthesis Finite Sequential Processes  . ...doi:10.1007/s11390-008-9196-x fatcat:br256bi5inf6divuhjkthk2kry
This paper surveys formal methods for specifying, designing and verifying real-time systems, so as to improve their safety and reliability. ... Safety critical computers increasingly a ect nearly every aspect of our lives. Computers control the planes we y on, monitor our health in hospitals and do our work in hazardous environments. ... Branching time temporal logics Linear time and branching time logics are incomparable. ...doi:10.1016/0164-1212(92)90045-l fatcat:zgh4zhmpjbbarecagzor3cxkh4
Lecture Notes in Computer Science
We present algorithms for the verification of skeletons and for the learning-based synthesis of skeletons from specifications in linear-time temporal logic (LTL). ... We present an analysis technique for temporal specifications of reactive systems that identifies, on the level of individual system outputs over time, which parts of the implementation are determined by ... Linear-time Temporal Logic: We use Linear-time Temporal Logic (LTL)  , with the usual temporal operators Next , Until U and the derived operators Eventually and Globally . ...doi:10.1007/978-3-319-46520-3_18 fatcat:yspl2qxqmbbgnhzsplgkwecyzq
This is due to the ability of these tools to take into account quite an amount of temporal and causal constraints and to employ resolution processes often designed to optimize the solution with respect ... This paper presents a preliminary report of the issues concerned with the use of two software tools for formal verification of finite state systems to the validation of the solutions produced by MrSPOCK ... Cesta and Fratini are also partially supported by European Space Agency (ESA) within the Advanced Planning and Scheduling Initiative (APSI). ...doi:10.1017/s0269888910000160 fatcat:ubmi4fgwere2zdtzd7bju7bjkm
Clarke, Using branching time temporal logic to synthesize synchronization skeletons Fairbairn, J., A new type-checker for a functional language Feather, MS., see Ph.E. ... Lei, Modalities for model checking: Branching t!me logic strikes back 8 (1987) 275 Emerson, E.A. and E.M. ...doi:10.1016/0167-6423(88)90074-3 fatcat:gnqque65m5ek7iuzgdu5rop5cq
The high quality of the synthetic motion demonstrates the effective design of our generator, and the discriminability of the synthesis also demonstrates the strength of our discriminator. ... This allows the use of such labels in supervising the training of the generator. We experiment with the SBU and the HHOI datasets. ... The major novelty of the system lies in the purposely designed generator module that model the spatial (i.e. joint movement) and temporal (i.e interaction synchronization) features of the reactive motion ...arXiv:2110.00380v1 fatcat:ew6e2oynuzbexopchgreqny3em
Within this logical framework, a basic planning methodology applying the discrete-event control synthesis methods is proposed and illustrated using TCT, a software design tool implementing these methods ... This basic result enables the application of the vast body of knowledge and associated synthesis tools already founded in discrete-event control theory for automatic coordination synthesis of distributed ... expressed in branching time temporal logic and alternating temporal epistemic logic, respectively. ...doi:10.1109/tcst.2008.924574 fatcat:fe4hdm4mfnbg5jqkzokjdeyzxe
The hardware translation is effectively implemented and used on the programmable active memory PerleO developed by J. Vuillemin and his group at Digital Equipment. ... I present a new hardware implementation of the pure synchronization subset of the language. Each program generates a specific circuit th at responds to any input in one clock cycle. ... Nesting temporal statements based on different time units is the main characteristic of the Esterel style. ...doi:10.1098/rsta.1992.0027 fatcat:2yhioiv5wnci5oxyq7ghixilby
In our approach, the logical specification of the component is given in dCTL-, a fragment of a branching time temporal logic with deontic operators, especially designed for fault-tolerant component specification ... Our technique for synthesis is based on the use of (bi)simulation algorithms for capturing different fault-tolerance classes, and the extension of a synthesis algorithm for CTL to cope with dCTLspecifications ... Acknowledgements First of all, I would like to express my deepest gratitude to my supervisor Tom Maibaum, for his advice, guidance, and encouragement throughout the course of this work. ...doi:10.1109/ase.2013.6693149 dblp:conf/kbse/Demasi13 fatcat:z7sidjnzrfdwnginmj7nujhcg4
At the end results are discussed and analyzed. ... After that model is interpreted as scheduling domain language and as predicate transition Petri net. Generated reachability tree presents search space with solutions. ... Some interpretation of solutions are: a) protocol synthesis b) SDL process: skeleton of program SDL can be generated and used by designer c) MSC skeleton processes can be composed in system. ...arXiv:1304.3716v1 fatcat:eyn5q5jor5elnemrym3c2h55zi
A,, Design and Synthesis of Synchronization Skeletons using Branching Time Temporal Logic, Proceedings of the IBM Workshop on Logics of Programs, Springer-Verlag Lecture Notes in ... ., Branching Time Synchronization TR-208, Univ. of in SCP) and Clarke, E. M., Using Logic to Synthesize Skeletons, Tech. Report Texas, 1982. (to appear and Halpern, J. ...doi:10.1145/567067.567081 dblp:conf/popl/EmersonH83 fatcat:peexmerl2zc7raffdcnn5tn5qe
The application of built-to-order embedded hardware designs in safety critical systems requires a high design quality and robustness during operation. ... The approach is demonstrated by showing the synthesis of an effective countermeasure against softwareinduced memory disturbance errors. ... The full standard includes linear and branching time properties, allowing the specification of complex safety and liveness properties. ...doi:10.1109/rsp.2015.7416550 dblp:conf/rsp/Chandrasekharan15 fatcat:verowjuxp5fczoamqbwwjdie7u
« Previous Showing results 1 — 15 out of 1,192 results