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Design and programming of embedded multiprocessors
2004
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04
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We present design technology for the structured design and programming of embedded multi-processor systems. ...
In [2] and [3] a library-based approach is proposed for generating hardware and software wrappers for the integration of heterogeneous sets of components. ...
ACKNOWLEDGEMENTS We acknowledge the contributions of Jeffrey Kang, Ondrej Popp, Dennis Alders, Avneesh Maheshwari, and Ghiath Alkadi from Philips Research and of Victor Reyes from the University of Las ...
doi:10.1145/1016720.1016771
dblp:conf/codes/WolfKHKE04
fatcat:us5r5qhr7regjjqappe25bklzq
Guest Editors' Introduction: Multiprocessor Systems-on-Chips
2005
Computer
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This is a central advantage of the HW/SW interface concept because without an efficient method to configure and optimize the HW/SW interface, the embedded system design cannot be mastered. ...
In "An Open Platform for Developing Multiprocessor SoCs," Mario Diaz Nava and coauthors describe a low-cost modular approach that uses emulation as an alternative to software simulation for the design ...
doi:10.1109/mc.2005.231
fatcat:ddegaas42zbkdlkgylycvyslqi
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors
[chapter]
2010
Lecture Notes in Computer Science
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Furthermore, in the presence of process variation, Maestro's wearout-centric scheduling outperformed both performance counter and temperature sensor based schedulers, achieving an order of magnitude more ...
This paper presents an introspective reliability management system, Maestro, to tackle reliability challenges in future chip multiprocessors (CMPs) head-on. ...
Center Research Program, a Semiconductor Research Corporation program. ...
doi:10.1007/978-3-642-11515-8_15
fatcat:bjxtgql7vbag5g57q3sqgnszee
Application Control and Monitoring in Heterogeneous Multiprocessor Systems
2018
2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
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Multiprocessor systems provide both highperformance and energy-efficient execution of applications on mobile and embedded systems under dynamic workload requirements, and can provide increased lifetime ...
This paper presents an analysis of applications, platforms and runtime management approaches to motivate the need for a standardised framework that enables fully applicationand platform-agnostic runtime ...
This approach can be generalised through a standardised software framework and the use of an application programming interface (API), to enable the exposure of control and monitoring sources from any application ...
doi:10.1109/recosoc.2018.8449379
dblp:conf/recosoc/LeechBBW18
fatcat:ehclt3eevfcynn6muvtoiadjea
Efficient Synchronization for Embedded On-Chip Multiprocessors
2006
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The SB also supports an efficient implementation of barriers. ...
Index Terms-Embedded systems, energy-aware systems, multiprocessor system-on-chip (MPSoC), network-on-chip (NoC), synchronization. ...
Zafalon of STMicroelectronics for encouraging this research. Finally, many thanks to E. Coffey for checking the final version of this paper. ...
doi:10.1109/tvlsi.2006.884147
fatcat:zb3s5gzdarf5tattdiioc6zxzy
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors
2006
2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
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Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. ...
The shared memory represents one of the key elements in designing MP-SoCs, since its function is to provide data exchange and synchronization support. ...
The authors of [8] present an algorithm to optimally solve the memory partitioning problem by dynamic programming. Regarding to multiprocessor systems, Kandemir et al. ...
doi:10.1109/icsamos.2006.300821
dblp:conf/samos/MonchieroPSV06
fatcat:cu6537637na4vgk3bfthdjxuoe
Exploiting shared scratch pad memory space in embedded multiprocessor systems
2002
Proceedings - Design Automation Conference
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In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. ...
Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. ...
Acknowledgments We acknowledge the support of the National Science Foundation through grants 0093082, 0073800, and 0121706. ...
doi:10.1145/513918.513974
dblp:conf/dac/KandemirRC02
fatcat:u75n2ozasfgqhlqsy3mdv3c4gi
Exploiting shared scratch pad memory space in embedded multiprocessor systems
2002
Proceedings - Design Automation Conference
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In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. ...
Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. ...
Acknowledgments We acknowledge the support of the National Science Foundation through grants 0093082, 0073800, and 0121706. ...
doi:10.1145/513972.513974
fatcat:itv4tcctqrf4rcwxuhicjfxk2i
Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures
2016
2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)
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Programming heterogeneous multiprocessor architectures is a real challenge when facing to a huge design space. ...
Computer-aided design and development tools try to circumvent this issue by simplifying instantiation mechanisms. ...
INTRODUCTION The design of embedded systems is facing two conflicting challenges. ...
doi:10.1109/mcsoc.2016.27
dblp:conf/mcsoc/RouxGSD16
fatcat:rpsqsmb6ovflvo6kcarz3w7y2y
Exploiting shared scratch pad memory space in embedded multiprocessor systems
2002
Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
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In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. ...
Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. ...
Acknowledgments We acknowledge the support of the National Science Foundation through grants 0093082, 0073800, and 0121706. ...
doi:10.1109/dac.2002.1012623
fatcat:mff2myoconev3gc2oitpd53hgm
Exploration of distributed shared memory architectures for NoC-based multiprocessors
2007
Journal of systems architecture
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Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. ...
The shared memory represents one of the key elements in designing MP-SoCs, since its function is to provide data exchange and synchronization support. ...
The authors of [8] present an algorithm to optimally solve the memory partitioning problem by dynamic programming. Regarding to multiprocessor systems, Kandemir et al. ...
doi:10.1016/j.sysarc.2007.01.008
fatcat:6jjvd42x2vetdmai3ftipxlg5e
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
2010
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems - LCTES '10
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In addition, our approach tries to reuse communication links across the different phases of the program to maximize link shutdown opportunities for the NoC (to satisfy power constraint). ...
Most of the prior software related work so far targeting CMPs focus on performance and power aspects. ...
Figure 15 . 15 Comparison of reliability centric, performance centric and energy centric formulations. ...
doi:10.1145/1755888.1755902
dblp:conf/lctrts/OzturkKIN10
fatcat:dtnxgyohzfasrk3cpl3ixxn3ii
Adaptive prefetching for shared cache based chip multiprocessors
2009
2009 Design, Automation & Test in Europe Conference & Exhibition
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Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. ...
evaluated in this paper using two embedded application codes. ...
ACKNOWLEDGMENT This research is supported in part by NSF Grants 0811687, 0720645, 0720749, and 0702519. ...
doi:10.1109/date.2009.5090768
dblp:conf/date/KandemirZO09
fatcat:6cfkzmzlrjdyljfe3lelq5b3y4
The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor
2007
International journal of parallel programming
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CMPs) become an exciting new direction by which system designers can deliver increased performance. ...
As CMOS feature sizes continue to shrink and traditional microarchitectural methods for delivering high performance (e.g., deep pipelining) become too expensive and power-hungry, chip multiprocessors ( ...
To ensure the right set of resources, application analysis was an important aspect of the design process, and the hardware and software design effort went hand in hand during the Cell BE development to ...
doi:10.1007/s10766-007-0035-4
fatcat:zcndew73k5bevgjnuc3h3lbtya
On-line dependability enhancement of multiprocessor SoCs by resource management
2010
2010 International Symposium on System on Chip
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This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. ...
This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. ...
The authors want to acknowledge the many contributions of all the other partners in the CRISP consortium, being Thales Netherlands, Atmel Automotive GmbH and Recore Systems. ...
doi:10.1109/issoc.2010.5625564
dblp:conf/issoc/BraakBHKVZ10
fatcat:ce7pe3kh35esbgneeobqbuay4i
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