Filters








136 Hits in 8.1 sec

Poster Presentation Abstracts

Scientific Committee
1969 Journal of cancer and allied specialties  
CT based image guided brachytherapy with HDR Ir-192 was carried out using brachyvision software on Gamma Med plus unit.  ...  Conclusions: Implementation of an electronic handoff tool in the absence of an EMR with minimal resources is a major breakthrough and can be replicated in other low-resource settings.  ...  As a proof of Concept, the DBE is implemented on an FPGA, and in the process of verification using the available thermograms, and will be implemented using 65nm standard CMOS process to achieve a power  ... 
doi:10.37029/jcas.v4i4.216 fatcat:dmrlbqxxoja3hd2ft6xekvtryu

Subframe multiplexing for FPGA manufacturing test configuration

Erik Chmelar
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
This paper presents an FPGA implementation for the Block Truncation Coding (BTC) image compression technique. Images are divided into equal blocks.  ...  For this work, an FPGA based ART extractor was designed and simulated for a Xilinx Virtex-E XCV300e in order to provide a speedup over software based extraction.  ...  Improving the Reliability of FPGA Circuits Using Triple-Modular Redundancy (TMR) & Efficient Voter Placement FPGA-Based Supercomputing: An Implementation for Molecular Dynamics An FPGA Prototype for  ... 
doi:10.1145/968280.968315 dblp:conf/fpga/Chmelar04 fatcat:bkkwooxvszbvlfrg4b7h5svtvi

Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study

Vincenzo Conti, Leonardo Rundo, Giuseppe Billeci, Carmelo Militello, Salvatore Vitabile
2018 Energies  
More specifically, the design methodology for the implemented digital signal processing application was adapted for the ZedBoard.  ...  Furthermore, this work introduces a hardware infrastructure and new energy metrics tailored for the energy efficiency evaluation of the dynamic partial reconfiguration process in embedded FPGA based devices  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/en11040739 fatcat:evjp2d35krat3jjsmxqv4o2vj4

Accessible near-storage computing with FPGAs

Robert Schmid, Max Plauth, Lukas Wenzel, Felix Eberhardt, Andreas Polze
2020 Proceedings of the Fifteenth European Conference on Computer Systems  
Secondly, we provide an integrated build process for FPGA overlay images that starts with the acquisition of compute kernels through a package manager and finally allows to dynamically configure near-storage  ...  The increased diversity of compute resources in turn affects programming models and practicalities of software development for near-data compute kernels and raises the question of how those resources can  ...  Acknowledgements We thank the anonymous reviewers and our shepherd, Tim Harris, for their valuable feedback.  ... 
doi:10.1145/3342195.3387557 dblp:conf/eurosys/SchmidPWEP20 fatcat:ykijhsup6jdpnkpcer2picfbfu

Proceedings of the ASP-DAC 2003. Asia and South Pacific Design Automation Conference 2003 (Cat. No.03EX627)

2003 Conference of Asia and South Pacific Design Automation 2003  
-chain Based Watch-points for Efficient Run-Time Debugging and Verification of FPGA Designs Anurag Tiwari, Karen A.  ...  Session) Presentation and Poster Session: University LSI Design ContestCo-chairs: Tomohisa Wada, Shoji Kawahito 6D-1 Design and Implementation of a Video-Oriented Network-Interface-Card System Ming-Chih  ... 
doi:10.1109/aspdac.2003.1194983 fatcat:obdbe4dwivgsfpbeuvb7s73fpe

On the Confidence in Bit-Alias Measurement of Physical Unclonable Functions

Florian Wilde, Michael Pehl
2019 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)  
The proposed methods are publicly available and should improve the design and evaluation of PUFs in the future.  ...  Physical Unclonable Functions (PUFs) are modern solutions for cheap and secure key storage.  ...  Our framework allows us to easily tune the accuracy-efficiency trade-off for an approximate design. We generate designs for RevLib and MCNC benchmarks, and basic image processing kernels.  ... 
doi:10.1109/newcas44328.2019.8961298 dblp:conf/newcas/WildeP19 fatcat:wv67uzuqlvcmhma3nahzdrr2ta

GCCE 2020 Subject Index

2020 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE)  
T U V W Self-Attention Based Neural Network for Few Shot Classification Self-Attention Based Neural Network for Few Shot Classification Separation of Multiple Sound Sources in the Same Direction  ...  Research for Unique Venue of Cultural Properties Made by Bricks in Japan Research on the Less Stress Acquisition Method for the Activity Information of Actual Residents Using the International Standard  ...  Framework Design and Implementation of Data Communication and Compression Methods in SIGMA Framework Design of a Data Auto-Select System Using Data Catalog for Smart Home Design of a Data Auto-Select  ... 
doi:10.1109/gcce50665.2020.9291796 fatcat:bmnnn7xnxrefhaneq262fe4i6u

Microprocessor Optimizations for the Internet of Things: A Survey

Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, Ann Gordon-Ross
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper provides a foundation for the analysis and design of a diverse set of microprocessor architectures for next-generation IoT devices.  ...  We then survey and discuss potential microarchitectural optimizations and computing paradigms that will enable the design of right-provisioned microprocessors that are efficient, configurable, extensible  ...  For example, Figure 3 depicts six nodes containing six different kinds of microprocessors: a single core in-order microprocessor (1-CPU), a 72-core general purpose GPU (72-GPU), a DSP, an FPGA, a quad-core  ... 
doi:10.1109/tcad.2017.2717782 fatcat:nnf5vx3sd5dq3ic2qjexvi6euq

ATIP/A*CRC Workshop on Accelerator Technologies for High-Performance Computing: Does Asia Lead the Way? Programme Handbook [article]

Michalewicz Marek, Kahaner David
2012 Zenodo  
It is an opportune time to analyze the current state-ofthe- art accelerated HPC architectures from an Asian perspective and experience, including practical issues of use, code development, and performance  ...  Additionally, we have arranged for site visits to some of Singapore's premier research labs and HPC centre in the universities.  ...  I will present OIST's existing data infrastructure and show new performance results for various file system options on this and newer hardware.  ... 
doi:10.5281/zenodo.3977457 fatcat:v2aftckqinasxk5ugdw27vinpa

Databases on Future Hardware (Dagstuhl Seminar 17101)

Gustavo Alonso, Michaela Blott, Jens Teubner, Marc Herbstritt
2017 Dagstuhl Reports  
The outcome of the seminar was not only a much better understanding of each other's needs, constraints, and ways of thinking.  ...  A number of physical limitations mandate radical changes in the way how we build computing hard-and software, and there is broad consensus that a stronger interaction between hard-and software communities  ...  Adaptive FPGA-based Database Accelerators -Achievements, Possibilities, and Challenges  ... 
doi:10.4230/dagrep.7.3.1 dblp:journals/dagstuhl-reports/AlonsoBT17 fatcat:nf7gedce45bfzlddmu6wm3gtpa

Vineyard In The Hipeac Newsletter Info 45 [article]

Christoforos Kachris
2016 Zenodo  
VINEYARD will develop an integrated platform for energy-efficient data centres based on new servers with novel, coarse-grain and fine-grain, programmable hardware accelerators.  ...  A consortium of HiPEAC (ICCS, Maxeler, QUB, FORTH and Neurasmus) and other partners have been granted a new H2020 project on customized and low-power data centers, called VINEYARD.  ...  Based on the abstracts, a panel of judges invite the most promising works to participate in a poster session.  ... 
doi:10.5281/zenodo.836718 fatcat:tktuvwkcgfhqpiyfzcqwsk5rny

Design of large polyphase filters in the Quadratic Residue Number System

Gian Carlo Cardarilli, Alberto Nannarelli, Yann Oster, Massimo Petricca, Marco Re
2010 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers  
FPXAs are abstract structures that can be targeted for implementation on applicationspecific integrated circuits, FPGAs, or other kinds of reconfigurable processors.  ...  implementation over DSP processors for reasons of higher sampling rates and more flexibility in design.  ... 
doi:10.1109/acssc.2010.5757589 fatcat:ccxnu5owr5fyrcjcqukumerueq

Hardware Developments Ii

Liang Liang, Jony Castagna, Alan O'Cais, Simon Wong, Goar Sanchez
2017 Zenodo  
detailed feedback to the project software developers; - discussion of project software needs with hardware and software vendors, completion of survey of what is already available for particular hardware  ...  Update on "Hardware Developments I" (Deliverable 7.1: https://doi.org/10.5281/zenodo.929533) which covers: - Report on hardware developments that will affect the scientific areas of interest to E-CAM and  ...  This would make the transition to new paradigms an implementation issue for the abstraction layer.  ... 
doi:10.5281/zenodo.1207612 fatcat:p75hwqe5jjantcugbqrov7ryla

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
2020 IEEE Access  
This work summarizes and compares the works for four leading platforms for the execution of algorithms such as CPU, GPU, FPGA and ASIC describing the main solutions of the state-of-the-art, giving much  ...  , explaining how to assess the quality of different networks and hardware systems designed for them.  ...  It is a high-level code abstraction for implementing NNs exploiting the lower level primitives of the corresponding framework.  ... 
doi:10.1109/access.2020.3039858 fatcat:nticzqgrznftrcji4krhyjxudu

Hardware Developments Iii

Alan Ó Cais, Liang Liang, Jony Castagna
2018 Zenodo  
and detailed feedback to the project software developers; - discussion of project software needs with hardware and software vendors, completion of survey of what is already available for particular hardware  ...  platforms; and, - detailed output from direct face-to-face session between the project endusers, developers and hardware vendors.  ...  This would make the transition to new paradigms an implementation issue for the abstraction layer.  ... 
doi:10.5281/zenodo.1304087 fatcat:itkihkoikvas5ajgxzqyswsez4
« Previous Showing results 1 — 15 out of 136 results