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Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Vijaykrishnan Narayanan, Chita R. Das
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology.  ...  butterfly, and concentrated mesh, respectively, for a 32-way CMP.  ...  They explored mesh and torus interconnects with different degrees of connectivity for generalized on-chip Networks.  ... 
doi:10.1109/hpca.2009.4798252 dblp:conf/hpca/DasEMVD09 fatcat:5r7vomk5p5fgbe5fqqotrkizvy

Physical-aware system-level design for tiled hierarchical chip multiprocessors

Jordi Cortadella, Javier de San Pedro, Nikita Nikitin, Jordi Petit
2013 Proceedings of the 2013 ACM international symposium on International symposium on physical design - ISPD '13  
At the early stages of the design of a CMP, physical parameters are often ignored and postponed for later design stages.  ...  Tiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-efficient many-core computing systems.  ...  Networks-on-chip Physical planning of a CMP is strictly driven by the organization of its on-chip interconnect. In this section we give a brief overview of the interconnect architecture.  ... 
doi:10.1145/2451916.2451920 dblp:conf/ispd/CortadellaPNP13 fatcat:ufzyr2nvlzg7zd4og7af4oe46u

Analytical Performance Modeling of Hierarchical Interconnect Fabrics

Nikita Nikitin, Javier de_San Pedro, Josep Carmona, Jordi Cortadella
2012 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip  
This paper proposes a scalable analytical method to estimate the performance of highly parallel CMPs (hundreds of cores) with hierarchical interconnect fabrics.  ...  The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem.  ...  Next section describes a simple example to emphasize the importance of contention in performance evaluation of hierarchical CMPs. Section III reports related work.  ... 
doi:10.1109/nocs.2012.20 dblp:conf/nocs/NikitinPCC12 fatcat:l77hcjtg4bbjnlbewyv5krxp4u

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Yoon-Jin Kim
2011 JSTS Journal of Semiconductor Technology and Science  
In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP.  ...  Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each  ...  evaluation of the hierarchical multiplexing interconnection structure.  ... 
doi:10.5573/jsts.2011.11.4.318 fatcat:dp74rlbbnfbhzfcggqymbnzt5q

Survey on Unified Inter/Intrachip Optical Network for Chip Multiprocessors

Priyanka Rajendran, Dr.Gnana Sheela K
2014 IOSR Journal of VLSI and Signal processing  
The results for eight real CMP applications show that on average UNION improves CMP performance by 3×while reducing 88% of network energy consumption.  ...  It connects not only cores on a single CMP, but also multiple CMPs in a system.  ...  Asaaf et al (2008) formulated the design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die [4] .  ... 
doi:10.9790/4200-04615261 fatcat:ckatiqftd5db5h4ug5b2zlsbra

Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors

Nikita Nikitin, Javier de San Pedro, Jordi Cortadella
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Based on this observation, a novel scalable analytical method is proposed to estimate the performance of highly parallel CMPs (hundreds or thousands of cores) with hierarchical interconnect networks.  ...  By using the analytical model as a performance and power estimator, an efficient metaheuristic-based search is proposed for the exploration of large design spaces.  ...  Kishinevsky, and U. Ogras for insightful comments and helpful discussions.  ... 
doi:10.1109/tcad.2013.2272539 fatcat:gvj6nwhgjje7fpaarfimg37mf4

A Dynamically Reconfigurable RF NoC for Many-Core

Alexandre Brière, Julien Denoulet, Andrea Pinna, Bertrand Granado, Francois Pêcheux, Eren Unlu, Yves Louët, Christophe Moy
2015 Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15  
With the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D.  ...  Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed.  ...  Results -Uniform On-Chip Traffic One of the most widely used traffic models for on-chip networks is the uniform model, where each node may generate a packet every cycle with a probability p.  ... 
doi:10.1145/2742060.2742082 dblp:conf/glvlsi/BriereDPGPULM15 fatcat:mdwycsmuuzajzbdqoerwu4esaq

ArchFP: Rapid prototyping of pre-RTL floorplans

Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
Current LMs include a generalized grid LM, one that supports geographic hints for component placement, and a fixed layout of imported subcomponents.  ...  There has been a fundamental shift from ever more complex single cores to single chip multi-core (CMP) designs.  ...  We also thank the anonymous reviewers for their helpful feedback.  ... 
doi:10.1109/vlsi-soc.2012.6379027 dblp:conf/vlsi/FaustZSSM12 fatcat:7uwpvuwlrzdm5gaihcycpdv3v4

ArchFP: Rapid prototyping of pre-RTL floorplans

Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
Current LMs include a generalized grid LM, one that supports geographic hints for component placement, and a fixed layout of imported subcomponents.  ...  There has been a fundamental shift from ever more complex single cores to single chip multi-core (CMP) designs.  ...  We also thank the anonymous reviewers for their helpful feedback.  ... 
doi:10.1109/vlsi-soc.2012.7332098 fatcat:yesazstuingepf232dvstyzonm

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors

S. Murali, D. Atienza, P. Meloni, S. Carta, L. Benini, G. De Micheli, L. Raffo
2007 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Designing an efficient network-on-chip (NoC)-based interconnect with predictable performance is thus a challenging task.  ...  Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality.  ...  (NoC) interconnection paradigms for multiprocessors system-on-chip, design automation, and low-power design.  ... 
doi:10.1109/tvlsi.2007.900742 fatcat:ruxhjmshgbdffdng7zfkpnxusy

A scalable micro wireless interconnect structure for CMPs

Suk-Bok Lee, Lixia Zhang, Jason Cong, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng, Mishali Naik
2009 Proceedings of the 15th annual international conference on Mobile computing and networking - MobiCom '09  
It makes the case for using a two-tier hybrid wireless/wired architecture to interconnect hundreds to thousands of cores in chip multiprocessors (CMPs), where current interconnect technologies face severe  ...  We also devise new two-tier wormhole based routing algorithms that are deadlock free and ensure a minimum-latency route on a 1000core on-chip interconnect network.  ...  David Wetherall and the anonymous reviewers for their constructive feedback. This work was supported in part by SRC grant #1796, and the U.S. Army Research Laboratory and the U.K.  ... 
doi:10.1145/1614320.1614345 dblp:conf/mobicom/LeeTPLCGRPNZC09 fatcat:fkelyqnjzndzxenh4uthc2dutu

An analysis of on-chip interconnection networks for large-scale chip multiprocessors

Daniel Sanchez, George Michelogiannakis, Christos Kozyrakis
2010 ACM Transactions on Architecture and Code Optimization (TACO)  
We evaluate and compare different network topologies using accurate simulation of the full chip, including the memory hierarchy and interconnect, and using a diverse set of scientific and engineering workloads  ...  With the number of cores of chip multiprocessors (CMPs) rapidly growing as technology scales down, connecting the different components of a CMP in a scalable and efficient way becomes increasingly challenging  ...  ACKNOWLEDGMENTS We sincerely thank Woongki Baek, Hari Kannan, Jacob Leverich, and the anonymous reviewers for their useful feedback on earlier versions of this manuscript.  ... 
doi:10.1145/1736065.1736069 fatcat:nbhnzmatgjbuzgffmji3wh6wey

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, David A. Wood
2005 SIGARCH Computer Architecture News  
The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers.  ...  We leverage an existing full-system functional simulation infrastructure (Simics [14]) as the basis around which to build a set of timing simulator modules for modeling the timing of the memory system  ...  We thank the University of Illinois for original beta testing.  ... 
doi:10.1145/1105734.1105747 fatcat:5vqwipjnrjfddmllpknvycdzz4

Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects

Sujay Deb, Amlan Ganguly, Kevin Chang, Partha Pande, Benjamin Beizer, Deuk Heo
2010 ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors  
In this paper a design methodology for a scalable hierarchical NoC with on-chip millimeter (mm)-wave wireless links is proposed.  ...  In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications.  ...  This level of transmitted power can be easily generated on-chip.  ... 
doi:10.1109/asap.2010.5540799 dblp:conf/asap/DebGCPBH10 fatcat:nhtvg77wxvfd5g3qrudlmil6uq

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

Xiaowen Wu, Yaoyao Ye, Jiang Xu, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Simulation results for eight real CMP applications show that on average UNION improves CMP performance by 3× while reducing 88% of network energy consumption.  ...  In this paper, we present a unified inter/intrachip optical network, called UNION, for chip multiprocessors (CMPs). UNION is based on recent progresses in nanophotonic technologies.  ...  UNION is a unified design with both on-chip and off-chip networks, whereas both Corona and Clos are only on-chip network designs.  ... 
doi:10.1109/tvlsi.2013.2263397 fatcat:muktjmzhafdc5e7jok4lud3ply
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