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Design and use of a program execution analyzer

L. R. Power
1983 IBM Systems Journal  
Design and use of a program execution analyzer Execution analyzers are used to improve the per- formance of programs, operating systems, and hardware systems.  ...  In addition, the design and use of a new program execution analyzer that we call the Experimental PL/I Execution Analyzer (EPLEA)' are discussed.  ... 
doi:10.1147/sj.223.0271 fatcat:nu3jlvgdsjfrtlp5rmw7qx26de

Proving the absence of run-time errors in safety-critical avionics code

Patrick Cousot
2007 Proceedings of the 7th ACM & IEEE international conference on Embedded software - EMSOFT '07  
We explain program correctness proofs by static analysis and the design of a static analyzer by abstract interpretation of a program semantics.  ...  None of the actual executions of the program being omitted, abstract-interpretation-based static analyzers have no false negatives hence are sound by design.  ...  We explain program correctness proofs by static analysis and the design of a static analyzer by abstract interpretation of a program semantics.  ... 
doi:10.1145/1289927.1289932 dblp:conf/emsoft/Cousot07 fatcat:mdv3xbuynzgrxmtiox3fuamf4u

A lab course on computer architecture

Pedro López, José Duato
1998 Proceedings of the 1998 workshop on Computer architecture education - WCAE '98  
They have been designed for a course length of 30 hours and they only require standard personal computers and some simulation tools.  ...  In this paper, the laboratory exercises for a course on computer architecture in the Computer Engineering degree at the Universidad Politécnica de Valencia are presented.  ...  Thus, it is not feasible to organize a lab course where the student has to design some hardware and then implement, analyze and debug it using a logic analyzer, or to learn a complex programming environment  ... 
doi:10.1145/1275182.1275193 dblp:conf/wcae/LopezD98 fatcat:acumg7ojzzby7nvh7d2gcbhhia


Yingtong Liu, Hsin-Wei Hung, Ardalan Amiri Sani
2020 Proceedings of the Fifteenth European Conference on Computer Systems  
Mousse uses novel solutions to overcome the above challenge. These include a novel processlevel SSE design, environment-aware concurrent execution, and distributed execution of program paths.  ...  Selective symbolic execution (SSE) is a powerful program analysis technique for exploring multiple execution paths of a program.  ...  The authors thank Felix Xiaozhu Lin and Zhiyun Qian for their invaluable feedback on an earlier draft of this paper.  ... 
doi:10.1145/3342195.3387556 dblp:conf/eurosys/LiuHS20 fatcat:yjd5njnvxrh7bfjfrlu3koh7ky

Page 143 of Journal of Aircraft Vol. 18, Issue 2 [page]

1981 Journal of Aircraft  
The versions of the main program used in PROSSS are those shown in Figs. 2a and c.  ...  Optimizer to Analyzer Processor The function of the O-A processor is to convert the design variables to a set of input parameters written in a format required by the analyzer.  ... 

Development of a System for Storing and Executing Bio-Signal Analysis Algorithms Developed in Different Languages

Moon-Il Joo, Satyabrata Aich, Hee-Cheol Kim
2021 Healthcare  
With the development of mobile and wearable devices with biosensors, various healthcare services in our life have been recently introduced.  ...  A significant issue that arises supports the smart interface among bio-signals developed by different vendors and different languages.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/healthcare9081016 fatcat:sxznamokhzctrm3eilo6t3rh5i

Effect Of Execution Time Analysis Epl Program For Computational Thinking Of Elementary School Students ^

Woojong Moon, Et. al.
2021 Turkish Journal of Computer and Mathematics Education  
By using the "Bebras Challenge" as an assessment tool and SPSS as a statistical tool, educational effects were analyzed through the results of pre- and post-computational thinking assessments.  ...  In this study, we developed and applied a primary educational programming language(EPL) program focused on execution time analysis aimed at improving computational thinking.  ...  ACKNOWLEDGMENTS This study was supported by the research grant of Jeju National University in 2020.  ... 
doi:10.17762/turcomat.v12i4.511 fatcat:gbgagsjsrvhbvmtm33o2syihhq

AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs

Biruk Mammo, Doowon Lee, Harrison Davis, Yijun Hou, Valeria Bertacco
2017 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)  
We encapsulate scenarios observed from diverse software executions into an abstract representation that can then be used to extract coverage models and generate test programs.  ...  To this end we analyze the behavior of software executed on high-level simulation models to identify commonly occurring accelerator interaction scenarios.  ...  Acknowledgments: This work was supported in part by C-FAR, one of the six SRC STARnet Centers, sponsored by MARCO and DARPA.  ... 
doi:10.1109/aspdac.2017.7858294 dblp:conf/aspdac/MammoLDHB17 fatcat:vc666tqpdjd3xlv77mcpyajvsm

A new framework for power estimation of embedded systems

C. Talarico, J.W. Rozenblit, V. Malhotra, A. Stritter
2005 Computer  
A proposed modular framework for assessing power consumption of embedded systems early in the design cycle can be extended to any performance metric and uses a high level of abstraction, leading to a faster  ...  Experimental results indicate that the approach is within 20 percent of gate-level estimation and executes three orders of magnitude faster.  ...  The main memory power analyzer and cache power analyzer also use this data to compute the power consumption of the main memory and cache accesses.  ... 
doi:10.1109/mc.2005.39 fatcat:a2uje35gifg7fk6qdsqhrxilt4

Decreasing defect rate of test cases by designing and analysis for recursive modules of a program structure: Improvement in test cases [article]

Muhammad Javed, Bashir Ahmad, Zaffar Abbas, Allah Nawaz, Muhammad Ali Abid, Ihsan Ullah
2012 arXiv   pre-print
In this paper, author proposed a strategy to design and analyze the test cases for a program structure of recursive modules.  ...  Designing and analysis of test cases is a challenging tasks for tester roles especially those who are related to test the structure of program.  ...  This FGN represent the all paths which can be used to analyze and design the test case for program.  ... 
arXiv:1208.5195v1 fatcat:g47jfaiognhypgjcrabxpzxpge

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

M. Irfan Uddin, Chris R. Jesshope, Michiel W. van Tol, Raphael Poss
2012 Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation Methods and Tools - RAPIDO '12  
architecture at less detailed level and allow the designer to make quick and reasonably accurate design decisions.  ...  ABSTRACT The current many-core architectures are generally evaluated by a detailed emulation with a cycle-accurate simulation of the execution time.  ...  In the rest of this paper, we use the shorthand SVP program to designate programs written in any language that supports the SVP protocol.  ... 
doi:10.1145/2162131.2162132 dblp:conf/rapido/UddinJTP12 fatcat:ylakm5gbfngazf4ngr7jcy3dfe

SAPA: Self-Aware Polymorphic Architecture [article]

Michel A. Kinsy, Mihailo Isakov, Alan Ehret, Donato Kava
2018 arXiv   pre-print
., the amount of parallelism in the program) and (2) automatic approximation to meet program and system goals (e.g., execution time budget, power constraints and computation resiliency) without the programming  ...  In this work, we introduce a Self-Aware Polymorphic Architecture (SAPA) design approach to support emerging context-aware applications and mitigate the programming challenges caused by the ever-increasing  ...  SELF-AWARE POLYMORPHIC ARCHITECTURE (SAPA) DESIGN For a computing system to automatically and dynamically adapt to program execution constraints, goals and phases, it needs to sense hardware states (a  ... 
arXiv:1802.05100v1 fatcat:txc5huhv2faqjmsawq55ujpfp4

Adaptable Structural Synthesis Using Advanced Analysis and Optimization Coupled by a Computer Operating System

J. Sobieszczanski-Sobieski, R. B. Bhat
1981 Journal of Aircraft  
The FSD procedure is executed in the programing system using analyzer in a loop shown in the flow chart in Fig. 6.  ...  Execution Options A variety of execution flows can be set up using the com- ponents described previously.  ... 
doi:10.2514/3.57475 fatcat:vjhwvoi7m5aozikq6bhrvjw2fu

A Survey of WCET Analysis of Real-Time Operating Systems

Mingsong Lv, Nan Guan, Yi Zhang, Qingxu Deng, Ge Yu, Jianming Zhang
2009 2009 International Conference on Embedded Software and Systems  
Timing correctness of hard real-time systems is guaranteed by schedulability analysis and worst-case execution time (WCET) analysis of programs.  ...  WCET tools designed for application program analysis have been applied to analyze RTOS routines by several research groups, but poor WCET estimations have been reported.  ...  The analysis tool uses a hybrid design with a tree representation of the control flow of the program and the execution time of each basic block obtained by measurement [30] .  ... 
doi:10.1109/icess.2009.24 dblp:conf/icess/LvGZDYZ09 fatcat:gtueqpoqy5ew5ptjkunsbx75t4

Execution Time Analysis for Embedded Real-Time Systems [chapter]

Andreas Ermedahl, Jakob Engblom
2007 Chapman & Hall/CRC Computer & Information Science Series  
Thus, knowing the execution-time characteristics of a program is fundamental to the successful design and execution of a realtime system [22, 57] .  ...  This chapter deals with the problem of how to estimate and analyze the execution time of embedded real-time software, in particular the worst-case execution time.  ...  Knowing the execution-time characteristics of a program is fundamental to the successful design and execution of a real-time system.  ... 
doi:10.1201/9781420011746.ch35 fatcat:eb2g33czavdrhp2e2kunv7vq2a
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