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Page 3868 of Mathematical Reviews Vol. , Issue 83i [page]

<span title="">1983</span> <i title="American Mathematical Society"> <a target="_blank" rel="noopener" href="https://archive.org/details/pub_mathematical-reviews" style="color: black;">Mathematical Reviews </a> </i> &nbsp;
Allen 831:68048 Design and synthesis of synchronization skeletons using branching time temporal logic. Logics of programs (Yorktown Heights, N.Y., 1981), pp. 52-71, Lecture Notes in Comput.  ...  From the introduction: “We propose a method of constructing concurrent programs in which the synchronization skeleton of the program is automatically synthesized from a high-level (branching time) temporal  ... 
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Towards Algorithmic Synthesis of Synchronization for Shared-Memory Concurrent Programs

Roopsha Samanta
<span title="2012-07-03">2012</span> <i title="Open Publishing Association"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qzezkwolyvf33pglm2jldjklca" style="color: black;">Electronic Proceedings in Theoretical Computer Science</a> </i> &nbsp;
The framework also supports synthesis of synchronization at different levels of abstraction and granularity.  ...  The specification language is an extension of propositional Computation Tree Logic (CTL) that enables easy specification of safety and liveness properties over control and data variables.  ...  Acknowledgements: The author wishes to thank Jyotirmoy Deshmukh for many insightful discussions during the course of writing this paper, and an anonymous reviewer for pointing out interesting future research  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.4204/eptcs.84.2">doi:10.4204/eptcs.84.2</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ny57q2e7lncihlbw7t7nkzny4a">fatcat:ny57q2e7lncihlbw7t7nkzny4a</a> </span>
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Page 3405 of Mathematical Reviews Vol. , Issue 83h [page]

<span title="">1983</span> <i title="American Mathematical Society"> <a target="_blank" rel="noopener" href="https://archive.org/details/pub_mathematical-reviews" style="color: black;">Mathematical Reviews </a> </i> &nbsp;
Allen Emerson, Design and synthesis of synchronization skeletons using branching time temporal logic (pp. 52-71); Robert L. Constable and Daniel R. Zlatin, The type theory of PL/CV3 (pp. 72-93); J.  ...  of concurrent programs: temporal proof principles (pp. 200-252); Zohar Manna and Pierre Wolper, Synthesis of communicating processes from temporal logic specifications (pp. 253-281); Albert R.  ... 
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Synthesizing Service Composition Models on the Basis of Temporal Business Rules

Jian Yu, Yan-Bo Han, Jun Han, Yan Jin, Paolo Falcarin, Maurizio Morisio
<span title="">2008</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5acgllsvrbf5dar4dbo3vyrz2a" style="color: black;">Journal of Computer Science and Technology</a> </i> &nbsp;
In this paper we present a framework and associated techniques to generate the process model of a service composition from a set of temporal business rules.  ...  Dedicated techniques including pathfinding, branching structure identification and parallel structure identification are used for semi-automatically synthesizing the process model from the semantics-equivalent  ...  For example, Beeck et al. use Semantic Linear-Time Temporal Logic to synthesis state charts [12] . Uchitel et al. use Message Sequence Charts to synthesis Finite Sequential Processes [27] .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s11390-008-9196-x">doi:10.1007/s11390-008-9196-x</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/br256bi5inf6divuhjkthk2kry">fatcat:br256bi5inf6divuhjkthk2kry</a> </span>
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Formal methods for the specification and design of real-time safety critical systems

Jonathan S. Ostroff
<span title="">1992</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/kqzhqyka2ffqdlbon77fd6trwm" style="color: black;">Journal of Systems and Software</a> </i> &nbsp;
This paper surveys formal methods for specifying, designing and verifying real-time systems, so as to improve their safety and reliability.  ...  Safety critical computers increasingly a ect nearly every aspect of our lives. Computers control the planes we y on, monitor our health in hospitals and do our work in hazardous environments.  ...  Branching time temporal logics Linear time and branching time logics are incomparable.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/0164-1212(92)90045-l">doi:10.1016/0164-1212(92)90045-l</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/zgh4zhmpjbbarecagzor3cxkh4">fatcat:zgh4zhmpjbbarecagzor3cxkh4</a> </span>
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Synthesizing Skeletons for Reactive Systems [chapter]

Bernd Finkbeiner, Hazem Torfah
<span title="">2016</span> <i title="Springer International Publishing"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
We present algorithms for the verification of skeletons and for the learning-based synthesis of skeletons from specifications in linear-time temporal logic (LTL).  ...  We present an analysis technique for temporal specifications of reactive systems that identifies, on the level of individual system outputs over time, which parts of the implementation are determined by  ...  Linear-time Temporal Logic: We use Linear-time Temporal Logic (LTL) [15] , with the usual temporal operators Next , Until U and the derived operators Eventually and Globally .  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-319-46520-3_18">doi:10.1007/978-3-319-46520-3_18</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/yspl2qxqmbbgnhzsplgkwecyzq">fatcat:yspl2qxqmbbgnhzsplgkwecyzq</a> </span>
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Validation and verification issues in a timeline-based planning system

Amedeo Cesta, Alberto Finzi, Simone Fratini, Andrea Orlandini, Enrico Tronci
<span title="2010-08-23">2010</span> <i title="Cambridge University Press (CUP)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ppliiwuwhjhjzdhxr5qnaaqsyi" style="color: black;">Knowledge engineering review (Print)</a> </i> &nbsp;
This is due to the ability of these tools to take into account quite an amount of temporal and causal constraints and to employ resolution processes often designed to optimize the solution with respect  ...  This paper presents a preliminary report of the issues concerned with the use of two software tools for formal verification of finite state systems to the validation of the solutions produced by MrSPOCK  ...  Cesta and Fratini are also partially supported by European Space Agency (ESA) within the Advanced Planning and Scheduling Initiative (APSI).  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1017/s0269888910000160">doi:10.1017/s0269888910000160</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ubmi4fgwere2zdtzd7bju7bjkm">fatcat:ubmi4fgwere2zdtzd7bju7bjkm</a> </span>
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Master index of volumes 1–10

<span title="">1988</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hq6x4whtd5hhlhsxzculyeamey" style="color: black;">Science of Computer Programming</a> </i> &nbsp;
Clarke, Using branching time temporal logic to synthesize synchronization skeletons Fairbairn, J., A new type-checker for a functional language Feather, MS., see Ph.E.  ...  Lei, Modalities for model checking: Branching t!me logic strikes back 8 (1987) 275 Emerson, E.A. and E.M.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/0167-6423(88)90074-3">doi:10.1016/0167-6423(88)90074-3</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/gnqque65m5ek7iuzgdu5rop5cq">fatcat:gnqque65m5ek7iuzgdu5rop5cq</a> </span>
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GAN-based Reactive Motion Synthesis with Class-aware Discriminators for Human-human Interaction [article]

Qianhui Men, Hubert P. H. Shum, Edmond S. L. Ho, Howard Leung
<span title="2021-10-01">2021</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
The high quality of the synthetic motion demonstrates the effective design of our generator, and the discriminability of the synthesis also demonstrates the strength of our discriminator.  ...  This allows the use of such labels in supervising the training of the generator. We experiment with the SBU and the HHOI datasets.  ...  The major novelty of the system lies in the purposely designed generator module that model the spatial (i.e. joint movement) and temporal (i.e interaction synchronization) features of the reactive motion  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2110.00380v1">arXiv:2110.00380v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ew6e2oynuzbexopchgreqny3em">fatcat:ew6e2oynuzbexopchgreqny3em</a> </span>
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Coordination Planning: Applying Control Synthesis Methods for a Class of Distributed Agents

Kiam Tian Seow, Manh Tung Pham, Chuan Ma, M. Yokoo
<span title="">2009</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/w55uhp5h3rdubpws6c5kic4vxm" style="color: black;">IEEE Transactions on Control Systems Technology</a> </i> &nbsp;
Within this logical framework, a basic planning methodology applying the discrete-event control synthesis methods is proposed and illustrated using TCT, a software design tool implementing these methods  ...  This basic result enables the application of the vast body of knowledge and associated synthesis tools already founded in discrete-event control theory for automatic coordination synthesis of distributed  ...  expressed in branching time temporal logic and alternating temporal epistemic logic, respectively.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcst.2008.924574">doi:10.1109/tcst.2008.924574</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fe4hdm4mfnbg5jqkzokjdeyzxe">fatcat:fe4hdm4mfnbg5jqkzokjdeyzxe</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170812043417/http://www3.ntu.edu.sg/home/asdrajan/ktseow3mar14/selected-papers/tcst-2009.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/dd/9e/dd9e1812602543d219012c44a3bdbce381faee29.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcst.2008.924574"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Esterel on hardware

Gérard Berry, John Edwin Field, Peter Gray
<span title="1992-04-15">1992</span> <i title="The Royal Society"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5iwetgsjafhghkg5csjfb64f7u" style="color: black;">Philosophical Transactions of the Royal Society of London Series A Physical and Engineering Sciences</a> </i> &nbsp;
The hardware translation is effectively implemented and used on the programmable active memory PerleO developed by J. Vuillemin and his group at Digital Equipment.  ...  I present a new hardware implementation of the pure synchronization subset of the language. Each program generates a specific circuit th at responds to any input in one clock cycle.  ...  Nesting temporal statements based on different time units is the main characteristic of the Esterel style.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1098/rsta.1992.0027">doi:10.1098/rsta.1992.0027</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/2yhioiv5wnci5oxyq7ghixilby">fatcat:2yhioiv5wnci5oxyq7ghixilby</a> </span>
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Synthesizing fault-tolerant programs from deontic logic specifications

Ramiro Demasi
<span title="">2013</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/hj24pr6lvba3dfi5muhp4mz5tm" style="color: black;">2013 28th IEEE/ACM International Conference on Automated Software Engineering (ASE)</a> </i> &nbsp;
In our approach, the logical specification of the component is given in dCTL-, a fragment of a branching time temporal logic with deontic operators, especially designed for fault-tolerant component specification  ...  Our technique for synthesis is based on the use of (bi)simulation algorithms for capturing different fault-tolerance classes, and the extension of a synthesis algorithm for CTL to cope with dCTLspecifications  ...  Acknowledgements First of all, I would like to express my deepest gratitude to my supervisor Tom Maibaum, for his advice, guidance, and encouragement throughout the course of this work.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ase.2013.6693149">doi:10.1109/ase.2013.6693149</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/kbse/Demasi13.html">dblp:conf/kbse/Demasi13</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/z7sidjnzrfdwnginmj7nujhcg4">fatcat:z7sidjnzrfdwnginmj7nujhcg4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170815093206/https://macsphere.mcmaster.ca/bitstream/11375/16234/3/Demasi_Ramiro_A_finalsubmission201408_PhD.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/c5/4c/c54c7f29cf8b5f3b503d0e995c289111efc77f5f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/ase.2013.6693149"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

From Declarative Model to Solution: Scheduling Scenario Synthesis [article]

Bruno Blaskovic, Mirko Randic
<span title="2013-04-12">2013</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
At the end results are discussed and analyzed.  ...  After that model is interpreted as scheduling domain language and as predicate transition Petri net. Generated reachability tree presents search space with solutions.  ...  Some interpretation of solutions are: a) protocol synthesis b) SDL process: skeleton of program SDL can be generated and used by designer c) MSC skeleton processes can be composed in system.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1304.3716v1">arXiv:1304.3716v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/eyn5q5jor5elnemrym3c2h55zi">fatcat:eyn5q5jor5elnemrym3c2h55zi</a> </span>
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"Sometimes" and "not never" revisited

E. Allen Emerson, Joseph Y. Halpern
<span title="">1983</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2qaxtqe2rfgjnfefqcokcnzelq" style="color: black;">Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages - POPL &#39;83</a> </i> &nbsp;
A,, Design and Synthesis of Synchronization Skeletons using Branching Time Temporal Logic, Proceedings of the IBM Workshop on Logics of Programs, Springer-Verlag Lecture Notes in  ...  ., Branching Time Synchronization TR-208, Univ. of in SCP) and Clarke, E. M., Using Logic to Synthesize Skeletons, Tech. Report Texas, 1982. (to appear and Halpern, J.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/567067.567081">doi:10.1145/567067.567081</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/popl/EmersonH83.html">dblp:conf/popl/EmersonH83</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/peexmerl2zc7raffdcnn5tn5qe">fatcat:peexmerl2zc7raffdcnn5tn5qe</a> </span>
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Ensuring safety and reliability of IP-based system design – A container approach

Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kuhne, Rolf Drechsler
<span title="">2015</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/vpx5dudvcrc7rbhkaxvb3bhjoi" style="color: black;">2015 International Symposium on Rapid System Prototyping (RSP)</a> </i> &nbsp;
The application of built-to-order embedded hardware designs in safety critical systems requires a high design quality and robustness during operation.  ...  The approach is demonstrated by showing the synthesis of an effective countermeasure against softwareinduced memory disturbance errors.  ...  The full standard includes linear and branching time properties, allowing the specification of complex safety and liveness properties.  ... 
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