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Design of interleaved multithreading for Network Processors on Chip

H.C. Freitas, F.L. Madruga, M. Alves, P. Navaux
2009 2009 IEEE International Symposium on Circuits and Systems  
NPoC (Network Processor on Chip) is a proposal to increase the performance of programmable NoC routers and multi-cluster NoC architectures using Interleaved Multithreading (IMT) technique.  ...  Therefore, the main goal of this paper is to present the design impact of interleaved multithreading for Network Processors on Chip focusing on area and performance feasibility.  ...  NPOC ARCHITECTURE NPoC was designed to increase flexibility and performance of NoC router architectures.  ... 
doi:10.1109/iscas.2009.5118237 dblp:conf/iscas/FreitasMAN09 fatcat:zgromdz24bfhxnfltptrjxcth4

A hybrid connector for efficient web servers

David Carrera, Vicenc Beltran, Jordi Torres, Eduard Ayguade
2008 International Journal of High Performance Computing and Networking  
We describe the implementation of this architecture on the Tomcat 5.5 server and evaluate its performance.  ...  In this paper we introduce a novel web server architecture that combines the best aspects of both the multithreaded and the event-driven architectures, the two major existing alternatives, to create a  ...  Acknowledgements This work is supported by the Ministry of Science and Technology of Spain and the European Union (FEDER funds) under contract TIN2007-60625.  ... 
doi:10.1504/ijhpcn.2008.025551 fatcat:eheit36g3zg7jkciq72wgemfie

Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC [chapter]

Sascha Uhrig
2009 Lecture Notes in Computer Science  
In this paper we evaluate the performance of different configurations of the same processor core within an SoPC: a single threaded single core, a multithreaded single core, a single threaded multicore,  ...  and a multithreaded multicore.  ...  The contribution of this paper is the simple design and the evaluation of a multithreaded multicore environment especially for embedded systems based on FPGAs.  ... 
doi:10.1007/978-3-642-03138-0_8 fatcat:j6hn5uvnqnbcnansg476yrte34

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
We examine many of these complexities and evaluate alternative organizations in the design space.  ...  Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor.  ...  Acknowledgments We would like to thank JohnO'Donnell from EquatorTechnologies, Inc. and Tryggve Fossum of Digital Equipment Corporation for access to the source for the Alpha AXP version of the Multiflow  ... 
doi:10.1145/285930.286011 dblp:conf/isca/TullsenEL98a fatcat:wzwmqqcnj5bz3faupjps7d6tay

Supporting multithreading in configurable soft processor cores

Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir
2007 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '07  
Using a suite of synthetic benchmarks, we evaluate five variations of MT-MB and show that multithreading is very effective in hiding the variable latencies associated with custom instructions and custom  ...  In this paper, we describe the organization and microarchitecture of MT-MB, a configurable implementation of the Xilinx MicroBlaze soft processor that supports multithreading.  ...  IMT-MB is a version of the Mi-croBlaze datapath designed to support n-way interleaved multithreading, and HMT-MB is a new datapath designed to implement a hybrid form of n-way interleaved and block multithreading  ... 
doi:10.1145/1289881.1289910 dblp:conf/cases/MoussaliGS07 fatcat:h7xmmjmc5nhgfldes2xt6fiosu

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1995 SIGARCH Computer Architecture News  
We examine many of these complexities and evaluate alternative organizations in the design space.  ...  Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor.  ...  Acknowledgments We would like to thank John O'Donnell from Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corporation for access to the source for the Alpha AXP version of the Multiflow  ... 
doi:10.1145/225830.224449 fatcat:gtheubj4tbcqxokcmbrfoihxym

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1995 Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95  
We examine many of these complexities and evaluate alternative organizations in the design space.  ...  Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor.  ...  Acknowledgments We would like to thank John O'Donnell from Equator Technologies, Inc. and Tryggve Fossum of Digital Equipment Corporation for access to the source for the Alpha AXP version of the Multiflow  ... 
doi:10.1145/223982.224449 dblp:conf/isca/TullsenEL95 fatcat:rj3illxasbalhkiz4ygcsjsvdi

The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures

R. Ubal, J. Sahuquillo, S. Petit, P. Lopez, J. Duato
2008 Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)  
In this paper, we evaluate the impact of retiring instructions out of order on different multithreaded architectures and different instruction fetch policies, using the recently proposed Validation Buffer  ...  Experimental results show that, for the same performance, out-of-order commit permits to reduce multithread hardware complexity (e.g., fine grain multithreading with a lower number of supported threads  ...  Our simulations are performed with a set of benchmark mixes, typically used for evaluation purposes on multithreading, and their results provide three main conclusions: (i) a fine-grain multithreaded VB-based  ... 
doi:10.1109/ipdps.2008.4536284 dblp:conf/ipps/UbalSPLD08 fatcat:evycgvofdfaljoxaqsjhcqwnim

Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors

Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir
2007 2007 International Conference on Field Programmable Logic and Applications  
These include a new thread scheduler that combines interleaved and block multithreading; a table of operation latencies (TOOL) for determining instruction latencies; support of arbitrary-latency custom  ...  This paper describes a number of microarchitectural techniques for supporting multithreading in soft processor cores.  ...  Then, in Section 4, we provide the results of our multithreaded processor implementations, and in Section 5 we evaluate the performance of the various implementations.  ... 
doi:10.1109/fpl.2007.4380768 dblp:conf/fpl/MoussaliGS07 fatcat:yqlxc23irzeifdgigwwfmaxyba

Part I: Special Issue on Parallel Architectures and Compilation Techniques

Jean-Luc Gaudiot
1996 International journal of parallel programming  
Koren have demonstrated a Mean Value Analysis model to evaluate the tradeoffs involved in the design of multiprocessors whose nodes are individual superscalar processors.  ...  The first paper, "Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution" by P-Y. Chang, E. Hao, Y. Patt, and P.  ...  Hall, and C-W. Tseng have concentrated on evaluating the influence of memory design on the performance of typical applications (such as can be found amongst SPEC or NAS, etc. benchmarks).  ... 
doi:10.1007/bf03356748 fatcat:4qjgh46xlvg5vd7tsgxqlele3u

Simultaneous thin-thread processors for low-power embedded systems

Won W. Ro, Jaeyoung Yi, Joon-Sang Park, Joonseok Park
2008 IEICE Electronics Express  
A drawback is that the conventional design of the superscalar processors possesses inherent complexity and power problems which are not easily acceptable in the domain of embedded processors.  ...  The traditional pipelined RISC processors have been the mainstream technology in high-end embedded systems; it is due to that embedded applications are often satisfied with minimum performance requirement  ...  Throughout the paper, the performance evaluation is performed on the ALPSS simulator [6] which has been designed based on the SimpleScalar 3.0 [1] and Wattch [2] .  ... 
doi:10.1587/elex.5.802 fatcat:axoa4v4bfje63hogzswwg3shci

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
2004 SIGARCH Computer Architecture News  
A single-ISA heterogeneous multi-core architecture is a chip multiprocessor composed of cores of varying size, performance, and complexity.  ...  This type of architecture covers a spectrum of workloads particularly well, providing high single-thread performance when thread parallelism is low, and high throughput when thread parallelism is high.  ...  This research was funded in part by NSF grant CCR-0105743 and a grant from Intel Corporation.  ... 
doi:10.1145/1028176.1006707 fatcat:rzncce5rfrfevanucuc5uwkulu

Development and Evaluation of an Experimental Java-based Web Server

Syed MutaharAaqib, Lalitsen Sharma
2013 International Journal of Applied Information Systems  
Objective of this paper is to present a model of a novel web server architecture based on the best properties of multithreaded and event-driven architectures.  ...  This paper then evaluates and compares its performance with Apache and μserver for both static and dynamic workloads.  ...  Former architecture is called multithreaded while as latter is referred as event-driven architecture. The multithreaded architectural model leads to a very simple and natural way of programming.  ... 
doi:10.5120/ijais12-450872 fatcat:xtsvt2sw6vbuzp3qrukwywvtvu

Evaluation of the SUN UltraSparc T2+ Processor for Computational Science [chapter]

Martin Sandrieser, Sabri Pllana, Siegfried Benkner
2009 Lecture Notes in Computer Science  
A set of benchmarks representing typical building blocks of scientific applications and a real-world hybrid MPI/OpenMP code for ocean simulation are used for performance evaluation.  ...  The intention of this evaluation is to investigate whether the current generation of massive chip multithreading processors is capable of providing competitive performance for non-server workloads in scientific  ...  The authors are grateful to Martin Wimmer for numerous discussions and helpful comments regarding the work presented in this paper.  ... 
doi:10.1007/978-3-642-01970-8_97 fatcat:ppz7trki6reptdqig5sqfm35ey

A Hybrid Web Server Architecture for Secure e-Business Web Applications [chapter]

Vicenç Beltran, David Carrera, Jordi Guitart, Jordi Torres, Eduard Ayguadé
2005 Lecture Notes in Computer Science  
In this paper we evaluate a novel hybrid web server architecture (implemented over Tomcat 5.5) that combines the best aspects of the two most extended server architectures, the multithreaded and the event-driven  ...  Designing a web server architecture that keeps these properties under high loads is a challenging task because they are the opposite to performance.  ...  Hybrid Architecture In this paper we evaluate a hybrid architecture that can take benefit of the strong points of both discussed architectures, the multithreaded and the event driven.  ... 
doi:10.1007/11557654_45 fatcat:jehdlcaylnenvfobonwewheuni
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