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Real-time DSP implementation of motion-JPEG2000 using overlapped block transferring and parallel-pass methods
2004
Real-time imaging
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Thus, it is very important to design and optimize these two modules in order to increase the performance of the hardware implementation. ...
This paper presents a real-time implementation of Motion-JPEG2000 encoder using a fixed-point DSP chip. ...
The core technology of MJP2 targets an intra-based coding system, which differs from the current moving pictures standards, MPEG (MPEG-1, 2 and 4). ...
doi:10.1016/j.rti.2004.08.003
fatcat:732faqbyxrgmhfvcglg5usllh4
FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study
2011
Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)
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The design of an embedded system based on the DPR functionality is still complex and tedious. The MPEG consortium proposes the Reconfigurable Video Coding (RVC) technology. ...
This paper studies the use of the RVC technology for the specification of an application and the design of a system based on the DPR functionality. ...
As we notice, partial reconfiguration is one of the useful solutions to reduce on chip area an increase performance, we use this technique to design an optimal implementation of RVC application. ...
doi:10.1109/dasip.2011.6136863
dblp:conf/dasip/HentatiANAD11
fatcat:pnfwsoldrbfnpk3o5mhh5oimni
VLSI architectures of perceptual based video watermarking for real-time copyright protection
2009
2009 10th International Symposium on Quality of Electronic Design
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The system is initially prototyped and validated in MATLAB/Simulink and subsequently implemented on an Altera Cyclone-II FPGA. ...
The watermark is inserted in the video stream before MPEG-4 compression, resulting in simplified hardware requirements and superior video quality. ...
Watermarking hardware systems are designed and implemented on an FPGA board, DSP board, or custom ICs. ...
doi:10.1109/isqed.2009.4810350
dblp:conf/isqed/MohantyKCR09
fatcat:bxhevnpaura2pi6d6sjtoqcqgi
Real-time perceptual watermarking architectures for video broadcasting
2011
Journal of Systems and Software
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The watermarked video is of high quality, with an average Peak-Signal-to-Noise Ratio (PSNR) of 21.8 dB and an average Root-Mean-Square Error (RMSE) of 20.6. ...
The system is initially simulated and validated in MATLAB/Simulink ® and subsequently prototyped on an Altera ® Cyclone-II FPGA using VHDL. ...
Acknowledgments The authors would like to thank Wei Cai and Manish Ratnani, graduates of the University of North Texas. This archival journal paper is based on our previous conference publication . ...
doi:10.1016/j.jss.2010.12.012
fatcat:bvgzzvisrngvpjwn5z736kwuo4
Use of Multiprocessing For High Throughput and Low Power Implementation of Two Dimensional Discrete Fourier Transform, Discrete Cosine Transform and MPEG Motion Estimation
2018
Biomedical Journal of Scientific & Technical Research
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In this work high throughput and low power implementations of two dimensional Discrete Fourier Transform, Discrete Cosine Transform and MPEG Motion Estimation, for battery powered real time applications ...
The results show the significance of multiprocessing in reducing the computational complexity of the application depending upon the type of application and the speed, area or power constraint. ...
In this parallelization an onchip memory (local memory of processor) equal to the length of a datablock is utilized, one memory block for real values and one memory block for imaginary values as shown ...
doi:10.26717/bjstr.2018.04.000981
fatcat:uppg2bkuxnfj7oinlbf2hqggze
A survey of media processing approaches
2002
IEEE transactions on circuits and systems for video technology (Print)
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We propose a categorization of existing microprocessors based on a combination of both architectural and functional flavors with examples of each approach from the latest multimedia processing families ...
These approaches can be broadly classified based on the evolution of processing architectures and the functionality of the processors. ...
on chip (SOC) and chipset-based implementations. • Exploration of memory issues ranging from fast high density and expensive on-chip RAMs to low-cost, high-speed, off-chip RAMs. • Evaluation of the cost ...
doi:10.1109/tcsvt.2002.800866
fatcat:2sgvuepvozda5k7jj67em6zeoq
Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications
2008
Journal of Visual Communication and Image Representation
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FPGA implementation. ...
This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. ...
The hardware design of the implemented AD calculation and the adder tree are based on a method proposed in [15] . ...
doi:10.1016/j.jvcir.2007.09.003
fatcat:45kdrdjt2rd47ejrgeltrbmk4q
Design and Implementation of Integer Transform and Quantization Processor for H.264 Encoder on FPGA
2009
2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies
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This paper proposes a novel implementation of the core processors, the integer transform and quantization for H.264 video encoder using an FPGA. ...
The complete H.264 video encoder was coded in Matlab in order to verify the results of the Verilog implementation. The processor is implemented on a Xilinx Vertex -II Pro XC2VP30 FPGA. ...
Section III deals with the architecture of the proposed schemes and Section IV with the implementation of the design in the FPGA. ...
doi:10.1109/act.2009.164
fatcat:m23u2u6qpvd2jnb6hdlwght7ku
A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs
2013
Circuits, systems, and signal processing
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The design was implemented on FPGA and later synthesized in CMOS 0.18 µm technology. ...
The results show that the proposed design satisfies the requirement of all codecs with a maximum decoding capability of 60 fps at 187.3 MHz for Xilinx Virtex4 LX60 FPGA of a 1080p HD video. ...
This design presents multi format video decoder which integrates AVS JP @ L6.2, H.264 HP @ L4.2, VC-1 AP @ L3 and MPEG-2 MP @ HL in a single chip and features resource sharing, memory management and early ...
doi:10.1007/s00034-013-9620-5
fatcat:hpdd5yu4xzcgtfs6jftlznol3i
Fractal engine: an affine video processor core for multimedia applications
1998
IEEE transactions on circuits and systems for video technology (Print)
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In this thesis, we propose the design of an affine video processor termed Fractal Engine. ...
Fractal Engine An Affine Video Processor Core for Multimedia Applications Abstract The recent advances in VLSI technology, high-speed processor designs, Intemethtranet implementations, broadband networks ...
Xiiinx FPGAs are typical exarnple of an SRAM FPGA.
this section different design tools are studied with an emphasis on logic synthesis. ...
doi:10.1109/76.735384
fatcat:sk2azaxd6je3nabiqjv5bfbrmy
An FPGA Implementation of HW/SW Codesign Architecture for H.263 Video Coding
[chapter]
2011
Effective Video Coding for Multimedia Applications
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Conclusions In this paper, we have described an efficient HW/SW codesign architecture of the H.263 video encoder into an embedded Linux environment. ...
Our architecture codes QCIF at 10-12.6 frames/sec with a 120 MHz system clock and can be improved with another FPGA platform having higher operating frequency. ...
Consequently, academia and industry have worked toward developing video compression algorithms [1] - [3] , which like ITU-T H.261, H.263, ISO/IEC MPEG-1, MPEG-2 and MPEG-4 emerged with a view to reduce ...
doi:10.5772/15469
fatcat:kj6wb7achbfl3oklljvzmrj2me
An FPGA implementation of HW/SW codesign architecture for H.263 video coding
2007
AEU - International Journal of Electronics and Communications
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Conclusions In this paper, we have described an efficient HW/SW codesign architecture of the H.263 video encoder into an embedded Linux environment. ...
Our architecture codes QCIF at 10-12.6 frames/sec with a 120 MHz system clock and can be improved with another FPGA platform having higher operating frequency. ...
Consequently, academia and industry have worked toward developing video compression algorithms [1] - [3] , which like ITU-T H.261, H.263, ISO/IEC MPEG-1, MPEG-2 and MPEG-4 emerged with a view to reduce ...
doi:10.1016/j.aeue.2006.11.001
fatcat:zwjf7sz45zhfzf66ayqcn6hslm
The Principle and Progress of Dynamically Reconfigurable Computing Technologies
2020
Chinese journal of electronics
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With the emergence of new applications and the increasing cost of new semiconductor manufacturing technology, high energy-efficiency and flexibility are both critical for processors. ...
This paper summarizes the latest progress in key technologies and provides an introduction of the application achievements. ...
This is also the approach taken by ASIC chips and FPGAs to implement a design. ...
doi:10.1049/cje.2020.05.002
fatcat:drwvb2el4zbc3mge4ytqtdx7z4
Subframe multiplexing for FPGA manufacturing test configuration
2004
Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04
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In particular, MPEG-7 provides a region based shape descriptor, the Angular Radial Transform (ART), for use in image and video annotation and retrieval. ...
For this work, an FPGA based ART extractor was designed and simulated for a Xilinx Virtex-E XCV300e in order to provide a speedup over software based extraction. ...
In this work we propose a reconfigurable software protection architecture that places an FPGA between the highest level of on-chip cache and main memory. ...
doi:10.1145/968280.968315
dblp:conf/fpga/Chmelar04
fatcat:bkkwooxvszbvlfrg4b7h5svtvi
The M2DC Project: Modular Microserver DataCentre
2016
2016 Euromicro Conference on Digital System Design (DSD)
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This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs. ...
Since their introduction, FPGAs can be seen in more and more different fields of applications. ...
On the other hand, the energy costs of large configurable switching knots can be reduced compared to CPU based implementations. ...
doi:10.1109/dsd.2016.76
dblp:conf/dsd/CecowskiAOKBCKP16
fatcat:bu4nbkqaejebjafrotibui6mkq
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