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P-sync: A Photonically Enabled Architecture for Efficient Non-local Data Access

David Whelihan, Jeffrey J. Hughes, Scott M. Sawyer, Eric Robinson, Michael Wolf, Sanjeev Mohindra, Julie Mullen, Anna Klein, Michelle Beard, Nadya T. Bliss, Johnnie Chan, Robert Hendry (+2 others)
2013 2013 IEEE 27th International Symposium on Parallel and Distributed Processing  
Communication in multi-and many-core processors has long been a bottleneck to performance due to the high cost of long-distance electrical transmission.  ...  The architecture is evaluated in the context of a non-local yet common application: the distributed Fast Fourier Transform.  ...  P-sync is evaluated analytically and experimentally in the context of a difficult yet common application kernel: the distributed Fast-Fourier Transform (FFT).  ... 
doi:10.1109/ipdps.2013.56 dblp:conf/ipps/WhelihanHSRWMMKBBCHBC13 fatcat:3qw2gowypndh7h32jynxnga7b4

Integrated photonic FFT for photonic tensor operations towards efficient and high-speed neural networks

Moustafa Ahmed, Yas Al-Hadeethi, Ahmed Bakry, Hamed Dalir, Volker J. Sorger
2020 Nanophotonics  
The algorithmic executing time is determined by the time-of-flight of the signal through this photonic reconfigurable passive FFT 'filter' circuit and is on the order of 10's of picosecond short.  ...  Here we present a silicon photonics-based architecture for convolutional neural networks that harnesses the phase property of light to perform FFTs efficiently by executing the convolution as a multiplication  ...  - Photonic CNN paradigm utilizing Fourier-optics based on integrated photonics. a, Block diagram of the photonic processor utilizing optical FFT to perform convolutions showing the data flow from the processor  ... 
doi:10.1515/nanoph-2020-0055 fatcat:2qqgbmvnd5de3lohohmyfwyz54

Integrated Photonic FFT for Optical Convolutions towards Efficient and High-Speed Neural Networks [article]

Moustafa Ahmed, Yas Al-Hadeethi, Ahmed Bakry, Hamed Dalir, Volker J. Sorger
2020 arXiv   pre-print
The algorithmic executing time is determined by the time-of-flight of the signal through this photonic reconfigurable passive FFT filter circuit and is on the order of 10s of picosecond.  ...  Here we present a silicon photonics-based architecture for convolutional neural networks that harnesses the phase property of light to perform FFTs efficiently by executing the convolution as a multiplication  ...  Figure 1 1 Figure 1 Figure 1 . 1 Photonic CNN paradigm utilizing Fourier-optics based on integrated photonics. a, Block diagram of the photonic processor utilizing optical FFT to perform convolutions  ... 
arXiv:2002.01308v2 fatcat:afdwwvct6zaqhkujtsicjb4nsa

Photonic NoCs: System-Level Design Exploration

Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni
2009 IEEE Micro  
It's therefore necessary to evaluate the photonic NoC performance using a physical-layer simulator working in tandem with a network simulator. 1 Such a design environment would provide the necessary  ...  The current Cell processor reportedly computes a large single-precision FFT (2 24 samples) in 43 ms using Bailey's FFT algorithm. 6 We assume that each core in our CMP corresponds to a future version  ... 
doi:10.1109/mm.2009.70 fatcat:3aozzuq73ndcvbkyjun75bihvq

Thermal management of manycore systems with silicon-photonic networks

Tiansheng Zhang, Jose L. Abellan, Ajay Joshi, Ayse K. Coskun
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
This paper first provides a design space exploration of silicon-photonic networks in manycore systems and quantifies the performance impact of the temperature gradients for various network bandwidths.  ...  Compared to existing workload allocation policies, the proposed policy improves system performance by up to 26.1% when running a single application and 18.3% for multi-program scenarios.  ...  Klamkin for helpful discussions on photonic device design and K. Kawakami for his contributions to thermal modeling. This work has been partially funded by the NSF grants CNS-1149703 and CCF-1149549.  ... 
doi:10.7873/date.2014.320 dblp:conf/date/ZhangAJC14 fatcat:jjs7ytsnsvhl3hjeitx3eqfzg4

Design Exploration of Optical Interconnection Networks for Chip Multiprocessors

Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni
2008 2008 16th IEEE Symposium on High Performance Interconnects  
cores, and (3) we present the first simulationbased assessment of the benefits of using a photonic NoC for a real application, i.e. computing a large FFT. * M.  ...  Building on this work, we study the adoption of photonic communication for CMPs and we present three main contributions: (1) we propose two nonblocking topologies for photonic NoC designs and we assess  ...  Comparing Photonic and Electronic NoCs. After evaluating the performance of the CMP with a photonic network, we consider the idea of replacing it with an equivalent electronic network.  ... 
doi:10.1109/hoti.2008.20 dblp:conf/hoti/PetraccaLBC08 fatcat:raqiysckxnacxl6rxk5a2eahne

Analysis of photonic networks for a chip multiprocessor using scientific applications

Gilbert Hendry, Shoaib Kamil, Aleksandr Biberman, Johnnie Chan, Benjamin G. Lee, Marghoob Mohiyuddin, Ankit Jain, Keren Bergman, Luca P. Carloni, John Kubiatowicz, Leonid Oliker, John Shalf
2009 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip  
photonic and electronic network designs.  ...  Results show that when utilizing standard process-to-processor mapping methods, this hybrid network can achieve 75× improvement in energy efficiency for synthetic benchmarks and up to 37× improvement for  ...  Acknowledgements This research is partially supported by DARPA MTO office under grant ARL W911NF-08-1-0127 and the National Science Foundation (Award #: 0811012).  ... 
doi:10.1109/nocs.2009.5071458 dblp:conf/nocs/HendryKBCLMJBCKOS09 fatcat:5mql6lbfajgu5ltexbr2euh7ei

Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing

Gilbert Hendry, Eric Robinson, Vitaliy Gleyzer, Johnnie Chan, Luca Carloni, Nadya Bliss, Keren Bergman
2010 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis  
In this work we develop a design for a photonic network-on-chip with integrated DRAM I/O interfaces and compare its performance to similar electronic solutions using a detailed network-on-chip simulation  ...  continues to widen due to the power and spatial constraints of electronic off-chip signaling.  ...  Designs of 4×4 photonic switches in the context of networks have been explored in [5] , but because a mesh router requires 5 ports (4 directions + processor core), we must reconsider the design of the  ... 
doi:10.1109/sc.2010.13 dblp:conf/sc/HendryRGCCBB10 fatcat:pfl5rku3fnfmhgwijzansf5yxi

FDOCT imaging processor for portable OCT systems with high imaging rate

Song-Nien Tang, Chih-Yu Hsiang, Sheng-Jie Huang, Wan-Wei Chen
2018 IEICE Electronics Express  
System-level design verification was performed using an FPGA platform and a mobile phone to evaluate the efficacy of the proposed scheme.  ...  This paper presents an image formation processor capable of performing all FDOCT imaging operations, including DC noise removal, re-sampling, realvalued fast Fourier transform (RFFT), and display processing  ...  Furthermore, a system-level experiment based on an FPGA platform and a mobile phone verified the efficacy of the proposed design.  ... 
doi:10.1587/elex.15.20171128 fatcat:yzp3gkhqlvh3zoayezbo2onqni

In-Fiber Fractional Signal Processing: Recent Results and Applications

Christian Cuadrado-Laborde, Luis Poveda-Wong, Antonio Carrascosa, Jose Luis Cruz, Antonio Diez, Miguel V. Andres
2018 2018 20th International Conference on Transparent Optical Networks (ICTON)  
The implementation of mathematical operators using photonic signal processing −as for example, conventional differentiators and integrators− is particularly well suited to overcome the speed and bandwidth  ...  Recently, we have been able to implement experimentally some of these theoretical proposals, and we have found specific applications for the 0.5 th -order differentiation and the photonic fractional Fourier  ...  A photonic signal processor has the ability to perform a certain operation directly on the complex field envelope of a given light signal.  ... 
doi:10.1109/icton.2018.8473797 fatcat:ryxtwwgfknb2flvbcaohjm7vl4

JADE

Rafael K. V. Maeda, Peng Yang, Xiaowen Wu, Zhe Wang, Jiang Xu, Zhehui Wang, Haoran Li, Luan H. K. Duong, Zhifei Wang
2016 Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems - AISTECS '16  
Due to its huge design space, evaluating candidate multicore architectures in early design stages, when the number of variables is at its maximum, is challenging.  ...  JADE simulation features include detailed electrical and optical interconnections, detailed memory hierarchy infrastructure, and built-in energy analysis allowing studies of a broad spectrum of systems  ...  Due to its huge design space, quickly evaluating its overall performance is of utmost importance to understand and evaluate such trade-offs.  ... 
doi:10.1145/2857058.2857066 dblp:conf/hipeac/MaedaYWW0WLDW16 fatcat:ogxjh6ztovh2zbsycxt76dnctq

Application development on hybrid systems

Roger D. Chamberlain, Mark A. Franklin, Eric J. Tyson, Jeremy Buhler, Saurabh Gayen, Patrick Crowley, James H. Buckley
2007 Proceedings of the 2007 ACM/IEEE conference on Supercomputing - SC '07  
A specific feature of the development environment is the availability of performance estimates (via simulation) prior to actual deployment on a physical system.  ...  Hybrid systems consisting of a multitude of different computing device types are interesting targets for high-performance applications.  ...  APPLICATION MAPPING AND PERFOR-MANCE EVALUATION To demonstrate the mapping, performance evaluation, and execution of an application onto a hybrid system, we examine a scientific application called "high-energy  ... 
doi:10.1145/1362622.1362690 dblp:conf/sc/ChamberlainFTBGCB07 fatcat:vqeje3bsb5cbfj4woq46euu7l4

Auto-pipe and the X language: a pipeline design tool and description language

M.A. Franklin, E.J. Tyson, J. Buckley, P. Crowley, J. Maschmeyer
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Auto-Pipe is a tool that aids in the design, evaluation and implementation of applications that can be executed on computational pipelines (and other topologies) using a set of heterogeneous devices including  ...  multiple processors and FPGAs.  ...  Auto-Pipe will be used in the system evaluation and design process. Figure 1 . 1 The Auto-Pipe design flow. A: X language,B: compilers,C: performance measurement, optimization, etc.  ... 
doi:10.1109/ipdps.2006.1639353 dblp:conf/ipps/FranklinTBCM06 fatcat:arprokqdpfchhbzyjf2pqgm2t4

Adaptive optics simulation performance improvements using reconfigurable logic

Alastair Basden
2007 Applied Optics  
The performance of parts of this simulation have been improved by up to 600 times (reducing computation times by this factor) by implementing algorithms within hardware and enables adaptive optics simulations  ...  The use of reconfigurable logic for high performance computing is currently in its infancy and has never before been applied to this field.  ...  Saunter and D. Geng for their thoughtful comments.  ... 
doi:10.1364/ao.46.000900 pmid:17279135 fatcat:ldkgjirzirbvpnambojcvubene

Numerical investigation of all-optical add-drop multiplexing for spectrally overlapping OFDM signals

S. Sygletos, S. Fabbri, E. Giacoumidis, M. Sorokina, D. M. Marom, M.F.C. Stephens, D. Klonidis, I. Tomkos, A. D. Ellis
2015 Optics Express  
We propose a novel architecture for all-optical add-drop multiplexing of OFDM signals.  ...  Sub-channel extraction is achieved by means of waveform replication and coherent subtraction from the OFDM super-channel.  ...  Acknowledgments This work has been supported by the Marie Currie -IEF project ARTISTE (IEF 330697), and the EU-ICT project FOX-C (grant number 318415).  ... 
doi:10.1364/oe.23.005888 pmid:25836815 fatcat:rdy5g7i7ffgx7geczxjl2czdy4
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