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RCBus: Row-Column Bus Topology for Optical Network-on-Chip

Weiwei Fu, Tianzhou Chen
2012 Elektronika ir Elektrotechnika  
The optical-electrical interface is also studied in the paper. The proposed optical network-on-chip can exploit the advantages of both photonic bus and direct torus topology.  ...  We use multiple write single-read schemes and virtual channel based token protocol to implement light-speed arbitration and flow control.  ...  Power estimation We use ORION [13] to estimate energy of on-chip electrical routers and links. For optical networks, laser and ring resonators are the main contributors to power consumption.  ... 
doi:10.5755/j01.eee.18.8.2633 fatcat:f4pr3ylytfazpcf6ufxsmxvonu

Chameleon: Channel efficient Optical Network-on-Chip

Sebastien Le Beux, Hui Li, Ian O'Connor, Kazem Cheshmi, Xuchen Liu, Jelena Trajkovic, Gabriela Nicolescu
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
However, the interface between electrical and photonic devices implies strong layout constraints that may impact the system performance and scalability.  ...  Compared to related networks, CHAMELEON demonstrates improved scalability and flexibility at the cost of minor increase in power consumption.  ...  WL ), number of on-chip lasers (N laser ), and number of MRs (N MR ) (NB: for Snake, the number of MRs takes into account both the MRs based filters in the receiver part of the network interface and the  ... 
doi:10.7873/date.2014.317 dblp:conf/date/BeuxLOCLTN14 fatcat:anaayyscqza4nieiyd3muqggje

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

Xiaowen Wu, Yaoyao Ye, Jiang Xu, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we present a unified inter/intrachip optical network, called UNION, for chip multiprocessors (CMPs). UNION is based on recent progresses in nanophotonic technologies.  ...  Simulation results for eight real CMP applications show that on average UNION improves CMP performance by 3× while reducing 88% of network energy consumption.  ...  Processors are grouped together by electrical networks on a chip, and they can access off-chip memory through optical channels.  ... 
doi:10.1109/tvlsi.2013.2263397 fatcat:muktjmzhafdc5e7jok4lud3ply

UNION: A unified inter/intra-chip optical network for chip multiprocessors

Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Jiang Xu
2010 2010 IEEE/ACM International Symposium on Nanoscale Architectures  
In this paper, we present a unified inter/intrachip optical network, called UNION, for chip multiprocessors (CMPs). UNION is based on recent progresses in nanophotonic technologies.  ...  Simulation results for eight real CMP applications show that on average UNION improves CMP performance by 3× while reducing 88% of network energy consumption.  ...  Processors are grouped together by electrical networks on a chip, and they can access off-chip memory through optical channels.  ... 
doi:10.1109/nanoarch.2010.5510930 dblp:conf/nanoarch/WuY0LNWX10 fatcat:65ctsqm2qbcavofpqodtfznwcq

A three-dimensional high-throughput architecture using through-wafer optical interconnect

D.S. Wills, W.S. Lacy, C. Camperi-Ginestet, B. Buchanan, H.H. Cat, S. Wilkinson, M. Lee, N.M. Jokerst, M.A. Brooke
1995 Journal of Lightwave Technology  
The network has been designed to meet off-chip U 0 using a new offset cube topology coupled with naming and routing schemes.  ...  Each integrated circuit layer contains analog interface circuitry, namely, detector amplifier and emitter driver circuitry, and digital circuitry for the network and/or processor, all of which are fabricated  ...  The router implements a simple adaptive routing strategy based on current local virtual-channel allocation.  ... 
doi:10.1109/50.390224 fatcat:tj2ovgtrjbdttlrf5qj5kbuhdi

Modeling a Photonic Network for Exascale Computing

Jose Duro, Salvador Petit, Julio Sahuquillo, Maria E. Gomez
2017 2017 International Conference on High Performance Computing & Simulation (HPCS)  
Photonics technology has become a promising and viable alternative for both on-chip and off-chip computer networks of future Exascale systems.  ...  Regarding the link configuration, the bandwidth per optical channel is the parameter with highest impact on the network delay and so on the execution time, while for a given optical bandwidth per channel  ...  ACKNOWLEDGMENTS This work was supported by the ExaNest project, funded by the European Union's Horizon 2020 research and innovation programme under grant agreement No 671553, and by the Spanish Ministerio  ... 
doi:10.1109/hpcs.2017.82 dblp:conf/ieeehpcs/DuroPSG17 fatcat:x2t77touurdnhkvdxim24gu2wu

Modeling A Photonic Network For Exascale Computing

Jose Duro, Salvador Petit, Julio Sahuquillo, Maria E. Gomez
2017 Zenodo  
Photonics technology has become a promising and viable alternative for both on-chip and off-chip computer networks of future Exascale systems.  ...  Regarding the link configuration, the bandwidth per optical channel is the parameter with highest impact on the network delay a [...]  ...  Moreover, silicon photonics-based on-chip networks enable the implementation of silicon photonic routers, which are a key development for inter-rack and intra-rack full-optical networks based only on optical  ... 
doi:10.5281/zenodo.823624 fatcat:f4ioahwrfjbpjcp4plvvgkp35q

Galaxy

Yigit Demir, Yan Pan, Seukwoo Song, Nikos Hardavellas, John Kim, Gokhan Memik
2014 Proceedings of the 28th ACM international conference on Supercomputing - ICS '14  
At the same time, the low latency and high bandwidth density of optical signaling maintain the tight coupling of cores, allowing the virtual chip to match the performance of a single chip that is not subject  ...  We propose Galaxy, an architecture that enables the construction of a many-core "virtual chip" by connecting multiple smaller chiplets through optical fibers.  ...  Because the optical links are traversed at most once, two Virtual Channels (VCs) are sufficient for the optical channels.  ... 
doi:10.1145/2597652.2597664 dblp:conf/ics/DemirPSHKM14 fatcat:x7xwkwwa7ncylkzhvw4p5sdefm

ATAC: Improving performance and programmability with on-chip optical networks

James Psota, Jason Miller, George Kurian, Henry Hoffman, Nathan Beckmann, Jonathan Eastep, Anant Agarwal
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
The new constraints and opportunities of on-chip optical interconnect are presented and explored in the design of ATAC.  ...  This paper introduces ATAC, a new manycore architecture that capitalizes on the recent advances in optics to address a number of challenges that future manycore designs will face.  ...  ATAC addresses these issues by integrating on-chip optical communication technologies to augment electrical communication channels.  ... 
doi:10.1109/iscas.2010.5537892 dblp:conf/iscas/PsotaMKHBEA10 fatcat:3buhnrvzivfvtli5643b5ncnhm

Exploiting New Interconnect Technologies in On-Chip Communication

John Kim, Kiyoung Choi, Gabriel Loh
2012 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
We provide an overview of the different technologies that are available and then, investigate how these interconnect technologies impact the architecture of the on-chip communication and the system design  ...  The conventional metal interconnect is limited, especially for global communication, and can not scale efficiently.  ...  Borkar [52] argued that with the large amount of wires available on-chip, a packet-switched network is not necessary and a bus-based interconnection network should be designed.  ... 
doi:10.1109/jetcas.2012.2201031 fatcat:3arzyh25zrcybaqc3sqlocus2q

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling

Chen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh, Vladimir Stojanovic
2012 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip  
In this paper, we present a tool, DSENT, for design space exploration of electrical and opto-electrical networks.  ...  While numerous opto-electronic NoCs have been proposed, their evaluations tend to be based on fixed numbers for both photonic and electrical components, making it difficult to co-optimize.  ...  DSENT MODELS AND TOOLS FOR PHOTONICS A complete on-chip photonic network consists of not only the photonic devices but also the electrical interface circuits and the tuning components, which dominate the  ... 
doi:10.1109/nocs.2012.31 dblp:conf/nocs/SunCKWMAPS12 fatcat:2h3iicffhvckrnnj4ltzgzp2pu

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Weichen Liu, Mahdi Nikdast
2012 ACM Journal on Emerging Technologies in Computing Systems  
Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs).  ...  THOE takes advantage of both electrical and optical routers and interconnects in a hierarchical manner.  ...  For comparing electronic torus-based NoC, electronic worm-hole switching is adopted, and in order to avoid deadlock, two virtual channels are used in each input port with a deadlock-free virtual channel  ... 
doi:10.1145/2093145.2093150 fatcat:nvdo2qss4vddjjeshzg4nugxai

100G beyond Ethernet transport for inter- and intra-DCN communication with solutions and optical enabling technologies in the ICT STRAUSS project

S. Yan, S. Peng, Y. Yan, B. R. Rofoee, Y. Shu, E. Hugues-Salas, G. Zervas, D. Simeonidou, M. Svaluto Moreolo, J. M. Fabrega, L. Nadal, Y. Yoshida (+11 others)
2015 2015 European Conference on Networks and Communications (EuCNC)  
A multi-domain optical infrastructure with end-toend Ethernet transport capability can deliver Ethernet services over a large scale and provide a promising solution for inter data center networks (DCN)  ...  In this paper, we report the work carried out in the ICT STRAUSS project to provide Ethernet connections for intra-DCN and inter-DCN over metro and core networks.  ...  This work is also partly funded by the Japanese Ministry of Internal Affairs and Communications (MIC) and National Institute of Information and Communications Technology (NICT) through the EU-Japan coordinated  ... 
doi:10.1109/eucnc.2015.7194097 dblp:conf/eucnc/YanPYRSHZSMFNYA15 fatcat:i7uxfbo6zrhrnozq7qwmwngyb4

Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures

Asmeen Kashif, Mohammed A. S. Khalid
2016 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)  
Designers typically choose copper interconnect on a printed circuit board (PCB) for chip-to-chip and chip-to-module interfaces.  ...  Generally, designers employ copper interconnect for chip-to-chip and chip-to-module interfaces over traces on a printed circuit board (PCB).  ... 
doi:10.1109/mwscas.2016.7869975 dblp:conf/mwscas/KashifK16 fatcat:hgpls6pryvfvpnsbwnvxup6o34

Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors [chapter]

Cheng Li, Paul V. Gratz, Samuel Palermo
2015 More than Moore Technologies for Next Generation Computer Design  
Gratz, and Samuel Palermo systems makes traditional electrical on-chip networks prohibitive for future transformative extrascale computers.  ...  Third, our photonic network architecture leverages the same wavelengths for channel arbitration and parallel data transmission, allowing efficient utilization of the photonic resources and lowering static  ...  Figure 5 shows the optical link budgets for the photonic data channel of Corona [21] , Firefly [19] , Clos [15] and LumiNOC under same radix and chip area, based on our power model (described in Section  ... 
doi:10.1007/978-1-4939-2163-8_7 fatcat:a46olb47unbxrgov5rcknn7sly
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