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Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
I-Fig. 5 : 5 Scheme A l (a) scheme A based on bulk devices (b) scheme A based on 3T-FinFETs Scheme C I Vgnd (e) scheme B based on 3T and 4T-(d) scheme C based on 3T and 4T-FinFETs (e) scheme D based on  ...  In this paper, we showed the inefficiency of source biasing for leakage reduction in 3T-FinFET SRAMs due to the absence of body effect.  ...  /FinFET devices, for high-performance logic and memory applications.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky

FinFETs: From Devices to Architectures

Debajit Bhattacharya, Niraj K. Jha
2014 Advances in Electronics  
We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.  ...  We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs.  ...  CCF-1217076 and CCF-1318603.  ... 
doi:10.1155/2014/365689 fatcat:wj3mk6blenfwtesg43n5qfevfq

HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy [article]

Sarabjeet Singh, Neelam Surana, Pranjali Jain, Joycee Mekie, Manu Awasthi
2021 arXiv   pre-print
In this paper, we propose a 'full-stack' solution to designing high capacity and low latency on-chip cache hierarchies by starting at the circuit level of the hardware design stack.  ...  We also observe dynamic energy savings of 42% and 34% for single- and multi-programmed workloads, respectively.  ...  [30] 4T GC [28] Proposed Total Transistors 6T 1T+1MTJ 1T+1PCM 1T+1C 2T 3T 4T 2T Area (um 2 access latency profiles [16] as compared to NVMs.  ... 
arXiv:2110.01208v2 fatcat:7lw63s7mmnd67htf3iruu7bbwm

2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26

2018 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
., see 2723-2736 , VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957  ...  Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J  ...  ., +, TVLSI April 2018 711-719 Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits.  ... 
doi:10.1109/tvlsi.2019.2892312 fatcat:rxiz5duc6jhdzjo4ybcxdajtbq

New Logic Synthesis as Nanotechnology Enabler

Luca Amaru, Pierre-Emmanuel Gaillardon, Subhasish Mitra, Giovanni De Micheli
2015 Proceedings of the IEEE  
We describe models and data-structures for logic design using emerging technologies and we show results of applying new synthesis algorithms and tools.  ...  The potentially large space for innovation has to be explored in the search for technologies that can support large-scale and highperformance circuit design.  ...  Acknowledgment The authors would like to thank their scientific collaborators for helping generating the experimental results, in particular: Mr  ... 
doi:10.1109/jproc.2015.2460377 fatcat:kakxk5w5q5bjlfgwirfyjnglwq

Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends

M. Lakshmi Varshika, Federico Corradi, Anup Das
2022 Electronics  
Current trends in neuromorphic technologies address the challenges of investigating novel materials, systems, and architectures for enabling high-integration and extreme low-power brain-inspired computing  ...  This review collects the most recent trends in exploiting the physical properties of nonvolatile memory technologies for implementing efficient in-memory and in-device computing with spike-based neuromorphic  ...  ., a flexible wearable memristor is designed with ammonium polyphosphate (APP) in a stack of Au/APP/ITO.  ... 
doi:10.3390/electronics11101610 fatcat:x4aqw2xk55g5tmdfqvygyxh5eu

Novel Approaches Toward Area- and Energy-Efficient Embedded Memories

Pascal Andreas Meinerzhagen
2014
for various great collaborations on the design, manufacturing, and measurement of many sub-V T memories based on custom-designed standard-cells.  ...  Jaydeep Kulkarni, who dedicated an amazing amount of his time to me (up to three 1:1 meetings per week), and from whom I learned tons in the field of analog and digital IC design, particularly in the field  ...  Therefore, in order to improve the access energy and the leakage power, the design of custom standard-cells focuses on leakage reduction.  ... 
doi:10.5075/epfl-thesis-6074 fatcat:4q3q7qy6p5f7nakakhkwyqmi2y