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Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays
2008
2008 Symposium on Application Specific Processors
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While most CGRA designs feature an array cell of the order of an ALU, this paper proposes a new kind of coarse grained array, called EGRA (Expression-Grained Reconfigurable Array), featuring a cell composed ...
A mapping methodology is proposed that can retargetably compile to a family of EGRAs, therefore enabling architectural exploration of the granularity of the proposed cell. ...
We call this cell RAC (Reconfigurable ALU Cluster), and the architecture that embeds it EGRA (Expression-Grain Reconfigurable Architecture). ...
doi:10.1109/sasp.2008.4570782
dblp:conf/sasp/AnsaloniBP08
fatcat:y72l6rz5eng25kmmdf4qu7dcly
EGRA: A Coarse Grained Reconfigurable Architectural Template
2011
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Index Terms-Coarse grained reconfigurable architectures (CGRAs), design space exploration. ...
We called the template expression-grained reconfigurable array (EGRA), as its ability to generate complex computational cells, executing expressions as opposed to single operations, is a defining feature ...
ACKNOWLEDGMENT The authors would like to thank the Advanced Learning and Research Institute (ALaRI), Lugano, Switzerland, for the technical support. ...
doi:10.1109/tvlsi.2010.2044667
fatcat:7psqlsnmb5g3flv2swuwtc6pny
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures
[chapter]
2000
Lecture Notes in Computer Science
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Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. ...
Based on the KressArray architecture family, a design-space exploration system is being implemented, which supports the designer in finding an appropriate architecture for a given application domain. ...
An architecture of the KressArray family is a regular array of coarse grain reconfigurable DataPath Units (rDPUs), each featuring a multiple-bit datapath and providing a set of coarse grain operators. ...
doi:10.1007/3-540-44614-1_42
fatcat:ks3tm2eb35eurkghtynfpbsnsi
A SLM-based overlay architecture for fine-grained virtual FPGA
2019
IEICE Electronics Express
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In this paper, we propose a fine-grained vFPGA overlay architecture that employs our previously proposed scalable logic module (SLM) as a logic cell. ...
+ FPGA respectively, as compared to a LUT-based vFPGA of the same input size. ...
The explored CWs and array sizes listed in Table I are the largest values of all implemented circuits on a certain architecture. ...
doi:10.1587/elex.16.20190610
fatcat:oftu3sal6ra5bc2rwxgkbdooqa
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures
[chapter]
2000
Lecture Notes in Computer Science
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Coarse-grain reconfigurable architectures promise to be more adequate for computational tasks due to their better efficiency and higher speed. ...
By comparative analysis of the results of a number of different experimental application-to-array mappings, the explorer system derives architectural suggestions. ...
An architecture of the KressArray family is a regular array of coarse grain reconfigurable DataPath Units (rDPUs), each featuring a multiple-bit datapath and providing a set of coarse grain operators. ...
doi:10.1007/3-540-45373-3_12
fatcat:fqupauzbcne5haq4dhqbfm7l5a
Guest Editorial Special Section on Configurable Computing Design—II: Hardware Level Reconfiguration
2008
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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The first paper of this group, "Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays," by P. ...
Experimental results show that the areas of these designs increase linearly with the number of types of operations in the expression and that the designs occupy less area and achieve higher throughput ...
His research interests include the design of high-performance application-specific processors, massively parallel computer systems, and reconfigurable architectures in mobile computing and multimedia applications ...
doi:10.1109/tvlsi.2007.914084
fatcat:v2hlvtqxgba6rplso6fgafve3a
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
2009
2009 Design, Automation & Test in Europe Conference & Exhibition
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To reduce this overhead, coarse-grained reconfigurable arrays (CGRAs) are reconfigurable at the ALU level, but a successful design needs more than computational power-the main bottleneck usually being ...
Just like the integration of hardwired multiplier and memory blocks enabled FPGAs to efficiently implement digital signal processing applications, in this paper we study a customizable architecture template ...
The evolution of coarse-grained architectures should not happen in isolation. ...
doi:10.1109/date.2009.5090723
dblp:conf/date/AnsaloniBP09
fatcat:twqcaz7vyzgqtnemo2ch2rqmqm
Mapping Applications onto Reconfigurable KressArrays
[chapter]
1999
Lecture Notes in Computer Science
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This paper introduces a design space explorer for coarse-grained reconfigurable KressArray architectures -to enable the designer to find out the optimal KressArray architecture for a given application. ...
This tool employs a mapper based on simulated annealing, and is highly configurable for a variety of different KressArray architectures. ...
Design Space Exploration An overview of the KressArray design space explorer is given in figure 2 . ...
doi:10.1007/978-3-540-48302-1_42
fatcat:aybfqupiove4nkl24guoone5y4
IJE special issue on reconfigurable hardware systems
2008
International journal of electronics (Print)
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The extreme flexibility of configurable and reconfigurable architectures, either implemented by fine-grain reconfigurable devices such as Field-Programmable Gate-Arrays (FPGAs) or coarse-grain reconfigurable ...
better architectural design quickly, by more easily navigating the inherent complexity of design space exploration exacerbated by the flexibility of configurable devices. ...
doi:10.1080/00207210801924461
fatcat:5gdrrfbuvze4fohnyvlqxodmfe
Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements
2007
2007 IEEE International Parallel and Distributed Processing Symposium
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This approach is able to identify sets of SSA instructions that can be mapped to different PE complexities available in coarsegrained reconfigurable computing architectures. ...
The method uses a three-address code SSA (static single assignment) representation of the kernel being mapped and Rewriting Logic for template matching and algebraic optimizations. ...
Acknowledgements This work has been possible due to the bilateral DAAD/CRUP cooperation project entitled "Architecture and Compilation Exploration for a Dynamically Reconfigurable System-on-Chip (ACER) ...
doi:10.1109/ipdps.2007.370369
dblp:conf/ipps/MorraCB07
fatcat:l662fewuojfmposck2bjarp7v4
Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain
2006
2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)
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Design decisions, such as type and ratio of functional units, strongly determine the later flexibility of domainspecific FPGAs and coarse-grained dynamically reconfigurable arrays. ...
For that reason the design of such reconfigurable architectures is done considering a set of target applications. ...
Conclusions We present a proposal to carry out the design space exploration when targeting coarse-grained domainspecific reconfigurable architectures. ...
doi:10.1109/reconf.2006.307755
dblp:conf/reconfig/FilhoSOKR06
fatcat:mdgmk4um6jfpzkbau53xnjehdq
Compiling custom instructions onto expression-grained reconfigurable architectures
2008
Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems - CASES '08
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We propose to target a different reconfigurable fabric, the EGRA (Expression-Grained Reconfigurable Array), to realize custom instructions in a customizable processor. ...
The compilation flow proposed is used here to efficiently explore the design space of the EGRA processing element; furthermore, its modularity and flexibility suggest suitability to generic CGRA retargetable ...
of RACs. introduced the Expression-Grained Reconfigurable Array (EGRA), featuring a new design for the processing element and enabling implementation of application-specific functional units in a customizable ...
doi:10.1145/1450095.1450106
dblp:conf/cases/BonziniAP08
fatcat:efoms7huvnbp5jwi6kgut4yr54
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
2009
Microprocessors and microsystems
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In this survey we explore the field of coarse-grained reconfigurable computing on the basis of the hardware aspects of granularity, reconfigurability, and interconnection networks, and discuss the effects ...
We classify the coarse-grained reconfigurable architectures into four categories and present some of the existing examples of these categories. ...
Veronica Gaspes, Jerker Bengtsson, Andreas Persson, and Prof. Dan Hammerstrom) for their valuable feedback during the internal review of the paper. ...
doi:10.1016/j.micpro.2008.10.003
fatcat:k4c63f4k2zbc5a4mfr3vfwqkfe
Reconfigurable and adaptive computing
2014
International journal of electronics (Print)
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The approach enabled fast design space exploration, rapid performance testing, and flexible programming of this kind of architecture. ...
with stripe-based coarse-grained reconfigurable architectures by drawing on insights from graph theory. ...
doi:10.1080/00207217.2014.938315
fatcat:dzrjhvgjcfbcldr2nuu6qqp5w4
High performance and area efficiency design of global register file for coarse-grained reconfigurable cryptographic processor
2016
IEICE Electronics Express
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The global register files (GRF) seriously affect performance and area of coarse-grained reconfigurable cryptographic processor (CGRCP). ...
By studying the direct factors affecting the performance of GRF and the characteristics of block cipher algorithms implemented on CGRCP, a distributed whole interconnected global register files (DWI-GRF ...
The base architecture adopted the same array size, operating behavior and other aspects, only changing the design parameters of GRF architecture. ...
doi:10.1587/elex.13.20160545
fatcat:ehstzc5c65g53dpyobwxdqlsgy
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