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Shuffle Exchange Network in Multistage Interconnection Network: A Review and Challenges

Nur Arzilawati Md Yunus, Mohamed Othman
2011 International Journal of Computer and Electrical Engineering  
Shuffle-exchange networks have been widely considered as practical interconnection systems due to their size of it switching elements and uncomplicated configuration.  ...  Multistage Interconnection Networks (MINs) are design to provide an effective communication in switching. MINs networks consist of stages that can route the switching through the path.  ...  Shuffle-exchange networks have been widely considered as practical interconnection systems due to their size of its SEs and uncomplicated configuration [5] .  ... 
doi:10.7763/ijcee.2011.v3.411 fatcat:77ejvgfdtvghxfk5f3hzfycj4e

Guest Editor's Introduction Interconnection Networks for Parallel and Distributed Processing

Bhuyan
1987 Computer  
Acknowledgments I would like to thank the authors and reviewers who helped to make this special issue a reality. They had severe time constraints and worked even during the Christmas holidays.  ...  Shriver, the editor-in-chief, for his constant guidance, encouragement, and help in the review process.  ...  The second article, by Kumar and Reddy, focuses on a particular faulttolerance technique that can be applied to shuffle exchange MINs.  ... 
doi:10.1109/mc.1987.1663585 fatcat:yxvykdw3uvcgtnzpgyu32cek54

Parallel Database Sort and Join Operations Revisited on Grids [chapter]

Werner Mach, Erich Schikuta
2007 Lecture Notes in Computer Science  
(see [1]) we develop a concise but comprehensive analytical model for the well-known Binary Merge Sort, Bitonic Sort, Nested-Loop Join and Sort Merge Join algorithm in a Grid Environment.  ...  Based on these results the paper proves that by smart enhancement exploiting the specifics of the Grid the performance of the algorithms can be increased and some results of Bitton et al. for a homogenous  ...  Each step consist of a comparison-exchange at every comparator module and a transfer to the target-comparator module. The comparator modules are connected by the perfect shuffle [11] .  ... 
doi:10.1007/978-3-540-75444-2_25 fatcat:5rt5ipnj6fcwpctkawc4nyc2hi

A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks

Oluwatosin Ahmed Amodu, Mohamed Othman, Nur Arzilawati Md Yunus, Zurina Mohd Hanapi
2021 Symmetry  
A particular class of these networks is shuffle exchange network (SEN) which involves a symmetric N-input and N-output architecture built in stages of N/2 switching elements each.  ...  This facilitates the realization of a highly efficient network design suitable for computational-intensive applications.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/sym13030378 fatcat:4bqwiubpb5anhcu7clri7eh4aq

A taxonomy of parallel sorting

Dina Bitton, David J. DeWitt, David K. Hsaio, Jaishankar Menon
1984 ACM Computing Surveys  
In the context of sorting networks, we describe two fundamental parallel merging schemes: the odd-even and the bitonic merge.  ...  We discuss sorting algorithms that evolved from these merging schemes for parallel computers, whose processors communicate through interconnection networks such as the perfect shuffle, the mesh, and a  ...  For each of these schemes one or several circuit topologms (linear array, mesh, binary tree, shuffle-exchange and cube-connected cycles, mesh of trees) are considered, and the resulting sorter is evaluated  ... 
doi:10.1145/2514.2516 fatcat:dc2bhjocynep5mfp3ntak3cfrq

Interconnection Networks Using Shuffles

P.-Y. Chen, D.H. Lawrie, P.-C. Yew, D.A. Padua
1981 Computer  
But the area required for the shuffle interconnection is proportional to (N/log N)2;18'19 thus, for the log-N-stage shuffle exchange network, the VLSI area would be at least N 2 /log N.  ...  Any multiprocessor system that employs more than one processor per job must be designed to allow efficient communication between processors, and between memories and processors, lest the advantages of  ... 
doi:10.1109/c-m.1981.220297 fatcat:fqwivvuws5g6thqiv7vciljwoy

Multistage Network With Globally Controlled Switching Stages and Its Implementation Using Optical Multi-Interconnection Modules

A. Cassinelli, M. Naruse, M. Ishikawa
2004 Journal of Lightwave Technology  
Performance analysis and simulation of a buffered GSMIN is also studied for packet routing purposes.  ...  This approach leads naturally to a MIN paradigm based not on cascading switching stages containing several size-reduced crossbars, as in the shuffle-exchange networks, but on cascading permutationreduced  ...  The authors would like to acknowledge two anonymous referees whose valuable comments have been helpful in improving the overall quality of the paper.  ... 
doi:10.1109/jlt.2004.824385 fatcat:tktmifel4nffji3xwyzbx4vc4y

Page 1632 of Mathematical Reviews Vol. , Issue 94c [page]

1994 Mathematical Reviews  
Summary: “In this paper, we propose a method for distributing data of an N x N matrix in an n-hypercube multiprocessor with N = 2" processors (m is even).  ...  The approach is based on a generalized multistage interconnection network (MIN) which is a generalization of the augmented shuffle- exchange MIN that we introduced previously [IEEE Trans.  ... 

DYRECT

Leslie D. Fife, Gopal Racherla, Steven E. Killian
1995 Proceedings of the 1995 workshop on Computer architecture education - WCAE-1 '95  
In this paper we discuss the design and implementation of a tool to teach dynamic reconfiguration of multicomputer systems.  ...  Various existing reconfiguration algorithms have been incorporated as a part of DYRECT's reconfiguration library. This tool allows the user to interactively design new reconfiguration algorithms.  ...  Acknowledgements The authors would like to thank the Graduate College and the School of Computer Science at the University of Oklahoma for research funding. Special thanks are due to Prof.  ... 
doi:10.1145/1275143.1275149 fatcat:yosxmpe26jglve2dhkaa5by354

An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

J. Sparso, H.N. Jorgensen, E. Paaske, S. Pedersen, T. Rubner-Petersen
1991 IEEE Journal of Solid-State Circuits  
Staunstrup for their continuous encouragement and tions.  ...  His main interests were circuit analysis, multiprocessor systems, speech synthe-Mr.  ...  SE interconnection network implementing both the shuffle interconnections shown in (a), and the exchange interconnections shown in (b).  ... 
doi:10.1109/4.68122 fatcat:glkhdysjynaonfogxc2ueugpyq

Study of multistage SIMD interconnection networks

Howard Jay Siegel, S. Diane Smith
1978 Proceedings of the 5th annual symposium on Computer architecture - ISCA '78  
Four SIMD multistage networks -Feng's data manipulator, STARAN flip network, omega network, and indirect binary n-cube --are analyzed~ Three parameters -topology, interchange box, and control structure  ...  Some problems may be solved more efficiently if the 2 n processing elements of an SIMD machine can be partitioned into submachines of size 2 r. Single and multiple control partitioning are defined.  ...  If only a shuffle and no exchange is allowed on each of the first n-r stages of the network, the network can serve as a complete r stage shuffle-e~change network for each of the 2 n-r groups of PE's of  ... 
doi:10.1145/800094.803052 dblp:conf/isca/SiegelS78 fatcat:wydlzs3hvrgi5bak2mqa26kona

The CUDA LATCH Binary Descriptor: Because Sometimes Faster Means Better [article]

Christopher Parker, Matthew Daiter, Kareem Omar, Gil Levi, Tal Hassner
2016 arXiv   pre-print
The design of LATCH makes it well suited for GPU processing. Owing to its small size and binary nature, the GPU can further be used to efficiently match LATCH features.  ...  Accuracy, descriptor size, and the time required for extraction and matching are all important factors when selecting local image descriptors.  ...  Then, pairs of threads simultaneously exchange their packed variables in a warp shuffle, and sum the result with their original variable.  ... 
arXiv:1609.03986v2 fatcat:tcbivmwjaraqfff5ralyotlnye

A Parallel State Assignment Algorithm for Finite State Machines [chapter]

David A. Bader, Kamesh Madduri
2004 Lecture Notes in Computer Science  
This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines.  ...  The SMPbased parallel algorithm -based on the sequential program JEDI targeting multilevel logic implementation -scales nearly linearly with the number of processors for FSMs of varying problem sizes chosen  ...  and hence, faster circuits with reduced size and power consumption, as well as faster execution times for the design and analysis.  ... 
doi:10.1007/978-3-540-30474-6_34 fatcat:chtp5wj4wrgt7pw27kxn54rqam

Fault tolerance in the Block-Shift Network

Yi Pan
2001 IEEE Transactions on Reliability  
Many popular networks such as the hypercube, the shuffle-exchange, and the complete networks, are instances of the BSN for different parameters.  ...  Future research includes more accurate reliability analysis for BSN, development of more efficient fault-tolerant routing algorithms, design and analysis of fault-tolerant broadcast algorithm and multicast  ...  Many popular networks such as the hypercube, the shuffle-exchange, and the complete networks are instances of the BSN for different parameters [21] , [22] , [24] .  ... 
doi:10.1109/24.935021 fatcat:oxmbacbwifhj3ggwazvxzvo44u

On exploring efficient shuffle design for in-memory MapReduce

Harunobu Daikoku, Hideyuki Kawashima, Osamu Tatebe
2016 Proceedings of the 3rd ACM SIGMOD Workshop on Algorithms and Systems for MapReduce and Beyond - BeyondMR '16  
MapReduce is commonly used as a way of big data analysis in many fields. Shuffling, the inter-node data exchange phase of MapReduce, has been reported as the major bottleneck of the framework.  ...  There are two types of shuffling algorithms for the conventional MapReduce implementations: Fully-Connected and more sophisticated algorithms such as Pairwise.  ...  Acknowledgements This work is partially supported by JST CREST "System Software for Post Petascale Data Intenseive Science" and JST CREST "Extreme Big Data (EBD) Next Generation Big Data Infrastructure  ... 
doi:10.1145/2926534.2926538 dblp:conf/sigmod/DaikokuKT16 fatcat:ajse3hzjffdmneykihztpktik4
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