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Design tradeoffs for software-managed TLBs

David Nagle, Richard Uhlig, Tim Stanley, Stuart Sechrest, Trevor Mudge, Richard Brown
1993 SIGARCH Computer Architecture News  
This work explores so@are-managed TM design tradeoffs and their interaction with a range of operating systems including monolithic and micnkwnel designs. 27uvugh haniwaw monitoring and simulatw~we explore  ...  Reducing the handling cost for kernel TLB mirses rvduces total TLB service time up to 40%. For TLBs between 32 and 128 slots, each a2Mbling of the TLB si.r,e reduces total TLB service time up to SO%.  ...  'lIds paper explores these issues by examining design tradeoffs for software-managed TLBs and their irnpac~in conjunction with various operating systems, on overall system performance.  ... 
doi:10.1145/173682.165127 fatcat:dwfzixda2re3fdntjheknj4dje

Design tradeoffs for software-managed TLBs

David Nagle, Richard Uhlig, Tim Stanley, Stuart Sechrest, Trevor Mudge, Richard Brown
1993 Proceedings of the 20th annual international symposium on Computer architecture - ISCA '93  
This work explores so@are-managed TM design tradeoffs and their interaction with a range of operating systems including monolithic and micnkwnel designs. 27uvugh haniwaw monitoring and simulatw~we explore  ...  Reducing the handling cost for kernel TLB mirses rvduces total TLB service time up to 40%. For TLBs between 32 and 128 slots, each a2Mbling of the TLB si.r,e reduces total TLB service time up to SO%.  ...  'lIds paper explores these issues by examining design tradeoffs for software-managed TLBs and their irnpac~in conjunction with various operating systems, on overall system performance.  ... 
doi:10.1145/165123.165127 dblp:conf/isca/NagleUSSMB93 fatcat:n5vjaeffyvh2xj4ly6dfmkss7q

Design tradeoffs for software-managed TLBs

Richard Uhlig, David Nagle, Tim Stanley, Trevor Mudge, Stuart Sechrest, Richard Brown
1994 ACM Transactions on Computer Systems  
Handling these misses substantially increases the cost of software-TLB management (Table VI). managed TLBs can be improved.  ...  OS IMPACT ON SOFTWARE-MANAGED TLBS Operating system references have a strong influence on TLB performance.  ... 
doi:10.1145/185514.185515 fatcat:nuya5frbwnhvvooxqa2eneb2wy

Address Translation Design Tradeoffs for Heterogeneous Systems [article]

Yunsung Kim, Guilherme Cox, Martha A. Kim, Abhishek Bhattacharjee
2017 arXiv   pre-print
This paper presents a broad, pathfinding design space exploration of memory management units (MMUs) for heterogeneous systems.  ...  We consider a variety of designs, ranging from accelerators tightly coupled with CPUs (and using their MMUs) to fully independent accelerators that have their own MMUs.  ...  CPU-Managed Address Translation We first examine the dynamics CPU-managed address translation.  ... 
arXiv:1707.09450v1 fatcat:fjvs3gq25nbspfgmyqlajetu6y

Architectural and organizational tradeoffs in the design of the MultiTitan CPU

N. P. Jouppi
1989 Proceedings of the 16th annual international symposium on Computer architecture - ISCA '89  
Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals.  ...  We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with  ...  Also, software to manage the write-back cache (e.g., flush I/O buffers to main memory) was already in place.  ... 
doi:10.1145/74925.74957 dblp:conf/isca/Jouppi89 fatcat:3kobxt37tfdg7igbosjwt6pnxy

Architectural and organizational tradeoffs in the design of the MultiTitan CPU

N. P. Jouppi
1989 SIGARCH Computer Architecture News  
Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals.  ...  We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with  ...  Also, software to manage the write-back cache (e.g., flush I/O buffers to main memory) was already in place.  ... 
doi:10.1145/74926.74957 fatcat:cib7kgqhyncyvaku3b6hsbdd6y

Agile Paging for Efficient Memory Virtualization

Jayneel Gandhi, Mark D. Hill, Michael M. Swift
2017 IEEE Micro  
Virtualization provides benefits for many workloads, but the overheads of virtualizing memory are still high.  ...  His research interests include computer architecture, operating systems, memory system design, virtual memory and virtualization.  ...  It proposes a hardware/software co-design called Agile Paging for fast virtualized address translation to address the needs of a wide variety of big-memory workloads.  ... 
doi:10.1109/mm.2017.67 fatcat:mkdx725jkncqzameskoah75ypm

Inter-core cooperative TLB for chip multiprocessors

Abhishek Bhattacharjee, Margaret Martonosi
2010 Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems - ASPLOS '10  
A number of past works have studied TLB designs to lower access times and miss rates, specifically for uniprocessors.  ...  We find that while a fully-hardware implementation results in average performance improvements of 8-46% for a range of TLB sizes, a hardware/software approach yields improvements of 4-32%.  ...  Acknowledgements We thank the anonymous reviewers for their feedback.  ... 
doi:10.1145/1736020.1736060 dblp:conf/asplos/BhattacharjeeM10 fatcat:hyxkdp3q5famjbelkz5hukc3km

Tradeoffs in fine-grained heap memory protection

Jianli Shen, Guru Venkataramani, Milos Prvulovic
2006 Proceedings of the 1st workshop on Architectural and system support for improving software dependability - ASID '06  
In this paper, we explore these tradeoffs for the purpose of heap security in order to discover whether the "right" granularity exists and how the granularity of protection affects design decisions.  ...  However, such protection can be done at different granularity(eg. perword, per-block, or per-page), with different performance, cost and memory overhead tradeoffs for different applications.  ...  Unfortunately, there have been relatively few studies of such fine-grain memory protection, especially when it comes to tradeoffs between hardware and software support.  ... 
doi:10.1145/1181309.1181317 dblp:conf/asplos/ShenVP06 fatcat:a76xwhdxujctlpjam3cl3eraua

Exploring Shared Virtual Memory for FPGA Accelerators with a Configurable IOMMU

Pirmin Vogel, Andrea Marongiu, Luca Benini
2019 IEEE transactions on computers  
We explore different TLB configurations and provide a comparison with other designs for shared virtual memory to gain insight on performance-critical IOMMU components.  ...  In this paper, we present a hardware/software framework for enabling transparent, shared virtual memory for FPGA accelerators in embedded SoCs.  ...  The authors would like to thank Somaje Maheshwara Sharma and Conrad Burchert for the valuable work during their master and student projects.  ... 
doi:10.1109/tc.2018.2879080 fatcat:aa3hescfwjawzcv4uj5bdyaepu

Efficient virtualization on embedded power architecture® platforms

Aashish Mittal, Dushyant Bansal, Sorav Bansal, Varun Sethi
2013 Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems - ASPLOS '13  
For example, workloads exhibiting a large amount of kernel activity typically show 3-5x slowdowns over bare-metal.  ...  Recent additions to the Linux kernel contain guest and host side paravirtual extensions for Power Architecture platforms.  ...  Acknowledgments We thank Stuart Yoder for helpful technical discussions on embedded Power Architecture processors.  ... 
doi:10.1145/2451116.2451163 dblp:conf/asplos/MittalBBS13 fatcat:blomlgsb4jd5ja4bjans6eka3m

Large pages and lightweight memory management in virtualized environments

Binh Pham, Ján Veselý, Gabriel H. Loh, Abhishek Bhattacharjee
2015 Proceedings of the 48th International Symposium on Microarchitecture - MICRO-48  
Our Generalized Large-page Utilization Enhancements (GLUE) allow system hypervisors to splinter large pages for agile memory management, while retaining almost all of the TLB performance of unsplintered  ...  This is because large pages often preclude lightweight memory management, which can outweigh their Translation Lookaside Buffer (TLB) benefits.  ...  ACKNOWLEDGMENTS We thank Jim Mattson for his help and valuable feedback. We thank Kathryn McKinley and Mark Hill for their insights and feedback in preparing the final version of the paper.  ... 
doi:10.1145/2830772.2830773 dblp:conf/micro/PhamVLB15 fatcat:5bcglr5xyvhcfm4y2vk3l7fahe

Architectural and Operating System Support for Virtual Memory

Abhishek Bhattacharjee, Daniel Lustig
2017 Synthesis Lectures on Computer Architecture  
A special thanks to Mike Morgan for his support of this book.  ...  On a personal note, we would like to thank Shampa Sanyal for enabling our research endeavors, and we would like to thank our respective families for making this all possible in the first place.  ...  SOFTWARE-MANAGED TLBS Page tables can be walked using either hardware or software support. In the early days of VM, software-managed TLBs using purely OS support for page table walks were the norm.  ... 
doi:10.2200/s00795ed1v01y201708cac042 fatcat:4re5afn53jhu7ezxwtb25ja3ca

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration [article]

Hasan Genc, Seah Kim, Alon Amid, Ameer Haj-Ali, Vighnesh Iyer, Pranav Prakash, Jerry Zhao, Daniel Grubb, Harrison Liew, Howard Mao, Albert Ou, Colin Schmidt (+7 others)
2021 arXiv   pre-print
Gemmini generates a wide design-space of efficient ASIC accelerators from a flexible architectural template, together with flexible programming stacks and full SoCs with shared resources that capture system-level  ...  Gemmini enables hardware designers to easily make these performance-efficiency tradeoffs.  ...  As shown in Figure 8a , we iterate over a variety of TLB sizes to find the design that best balances TLB overhead and overall performance, including over a design point where the shared L2 TLB has zero  ... 
arXiv:1911.09925v3 fatcat:yftbmax3c5dqtfvovhyz57oihy

Using Write Protected Data Structures To Improve Software Fault Tolerance in Highly Available Database Management Systems

Mark Sullivan, Michael Stonebraker
1991 Very Large Data Bases Conference  
This paper describes a database management system (DBMS) modified to use hardware write protection to guard critical DBMS data structures against software errors.  ...  Read-write data structures can be guarded as long as correct software is able to temporarily unprotect the data structures during updates.  ...  update model can be implemented on any processor which uses a software-loaded TLB. Of course, guarding is designed to protect against accidental damage not malicious damage.  ... 
dblp:conf/vldb/SullivanS91 fatcat:p4sc5cfzavfgpdvpn4alzbc66m
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