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Formal Techniques for Effective Co-verification of Hardware/Software Co-designs

Rajdeep Mukherjee, Mitra Purandare, Raphael Polig, Daniel Kroening
2017 Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17  
To address these limitations, we present an approach that uses a bounded co-verification tool, HW-CBMC, for formally validating hardware/software co-designs written in Verilog and C.  ...  Verification is indispensable for building reliable of hardware/software co-designs. However, the scope of formal methods in this domain is limited.  ...  The TAA is a co-design in which the SW sends documents or streams of data packets to the FPGA for analysis and reacts to the response of the HW.  ... 
doi:10.1145/3061639.3062253 dblp:conf/dac/MukherjeePPK17 fatcat:wue4lpkurvaztggpajrunldwvm

Accelerating System Verilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator

Abhishek Jain, Piyush Kumar Gupta, Hima Gupta, Sachish Dhar
2013 International Journal of VLSI Design & Communication Systems  
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly  ...  In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog and their usage in UVM based Verification Environment of Image Signal Processing designs to increase  ...  guidance and support.  ... 
doi:10.5121/vlsic.2013.4602 fatcat:f5gfwr4sxzazjl6zsqnx54skpi

A systematic IP and bus subsystem modeling for platform-based system design

Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim
2006 Proceedings of the Design Automation & Test in Europe Conference  
IP Modeling and Verification Code reusability: We separate the functional and communication parts of each IP model to achieve systematic code reusability, as shown in Fig. 1 .  ...  The topic on platform-based system modeling has received a great deal of attention today.  ...  Kim is supported by the Ministry of Science and Technology / Korea Science and Engineering Foundation through the Advanced Information Technology Research Center (AITrc).  ... 
doi:10.1109/date.2006.243954 dblp:conf/date/UmKHKCKEK06 fatcat:7zoi7zd6gjhqlaoqi6haz4lh7u

A Path Construction Algorithm for Translation Validation Using PRES+ Models

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal, Kunal Banerjee, Krishnam Raju Duddu
2016 Parallel Processing Letters  
Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks.  ...  A BDD based Secure Hardware Design Method to Guard Against Power Analysis Attacks. International Symposium on VLSI Design and Test (VDAT), Coimbatore, India, 2014, pages: 1-2. 10.  ... 
doi:10.1142/s0129626416500109 fatcat:wvfslscsbvab5c6h7ase5423ny

Equivalence Checking Using Trace Partitioning

Rajdeep Mukherjee, Daniel Kroening, Tom Melham, Mandayam Srivas
2015 2015 IEEE Computer Society Annual Symposium on VLSI  
One application of equivalence checking is to establish correspondence between a high-level, abstract design and a low-level implementation.  ...  We propose a new partitioning technique for the case in which the two designs are substantially different and traditional equivalence-point insertion fails.  ...  All these techniques are tuned for the case of equivalence verification of structurally identical designs [7] , [8] .  ... 
doi:10.1109/isvlsi.2015.110 dblp:conf/isvlsi/MukherjeeKMS15 fatcat:vexrgnkqsvg7fpj47nomdbvgom

A SystemC-only design methodology and the CINE-IP multimedia platform

Guido Araújo, Edna Barros, Elmar Melcher, Rodolfo Azevedo, Karina R. G. da Silva, Bruno Prado, Manoel E. de Lima
2005 Design automation for embedded systems  
The IPP Verification Methodology (IPV) is based on a careful refinement of the SystemC behavioral description towards RTL.  ...  The application of the IPP methodology in the design of CINE-IP, and its impact in design productivity is thoroughly analyzed. Keywords A based on SystemC design methodology .  ...  In this paper, we describe a SystemC-based IP-core design process, called IP PROCESS (IPP) [9] . IPP is inspired on a rigorous software design process and co-verification methodology.  ... 
doi:10.1007/s10617-006-9585-8 fatcat:cf5idt3zxzeobkxobf3mykkxrq

Some common aspects of design validation, debug and diagnosis

T. Arnaout, G. Bartsch, H.J. Wunderlich
2006 Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)  
Design, Verification and Test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnostic resolution.  ...  Diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping.  ...  CONCLUSIONS Today's complex designs require special structures to allow validation and verification.  ... 
doi:10.1109/delta.2006.79 dblp:conf/delta/ArnaoutBW06 fatcat:46msbnlemjdpxezf4vp4j6zjle

A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware

Sungpack Hong, Tayo Oguntebi, Jared Casper, Nathan Bronson, Christos Kozyrakis, Kunle Olukotun
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
This paper presents an interesting system-level co-design and co-verification case study for a non-trivial design where multiple high-performing x86 processors and custom hardware were connected through  ...  Lessons from our study can similarly be applied to design and verification of other tightly-coupled systems.  ...  DESIGN AND VERIFICATION Target Design This section outlines the design of our system for the sake of providing sufficient background context for one to understand our co-design and co-verification issues  ... 
doi:10.1145/2380445.2380524 dblp:conf/codes/HongOCBKO12 fatcat:4jgtca2j6nbyrhhb2na7q2li7m

A Design of AMBA AXI4-Lite ACE Interconnect Protocol for Transactionbased SoC Design Techniques Integration

Chiranjeet Kumar, Dr. M. Gurunadha Babu
2017 International Journal Of Engineering And Computer Science  
The usage of the transaction based techniques are designed for the software analysis and for the first time, in this research work it is used for the physical hardware design and its analysis based on  ...  The proposed methodology is useful for the hardware design engineers to deal with the complexity simplification issues by bringing the benefits of transaction-based verification (TBV) to it approach.  ...  Adopting Transaction-level modeling (TLM) technique and developing intellectual properties (IP) and flexible automated tools for design as well as verification are some of the methods which are targeted  ... 
doi:10.18535/ijecs/v6i6.53 fatcat:mkm5atrxlrejjbhjzhud3vtjua

Virtual Prototyping Platform for Multiprocessor System-on-Chip Hardware/Software Co-design and Co-verification [chapter]

Arya Wicaksana, Tang Chong Ming
2017 Studies in Computational Intelligence  
This paper describes the implementation of a virtual prototyping platform to address the ever-challenging multiprocessor system-on-chip (MPSoC) hardware/software co-design and co-verification requirements  ...  One approach is to raise the abstraction level of system design and verification to ESL.  ...  Lee Sze Wei, and Mr. Ng Mow Song for the support of this research, for the encouragement, enthusiasm, and immense knowledge. This would not have been possible without their guidance and support.  ... 
doi:10.1007/978-3-319-60170-0_7 fatcat:b652rfjyznhehe4xf3lfrygche

Guest Editorial: Special Issue On Emerging Technologies in Computer Design

Ozgur Sinanoglu, Umit Ogras
2021 IEEE Transactions on Emerging Topics in Computing  
IP and platform-based designs; HW/SW co-design; Modeling and performance analysis; Support for security, languages and operating systems; Hardware/software techniques for embedded systems; Application-specific  ...  Electronic Design Automation: High-level, logic and physical synthesis; Physical planning, design and early estimation for large circuits; Automatic analysis and  ...  optimization of timing, power and noise; Tools for multiple-clock domains, asynchronous and mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DFM  ... 
doi:10.1109/tetc.2020.3046058 fatcat:h7e5cwrpgjdevem6isdljiuz6i

Design challenges for high performance nanotechnology

G. Debnath, P. Thadikaran
2006 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)  
It will capture the design issues in the areas of high level architectural modeling, design for manufacturability (DFM), layout synthesis, standard cell design, and performance verification.  ...  This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology.  ...  . • Design-for-Test challenges that addresses DFT strategy and planning, Fault models, Full/partial scan design, and special test structures. • Performance verification that describes the limitation of  ... 
doi:10.1109/vlsid.2006.64 dblp:conf/vlsid/DebnathT06 fatcat:p5ugv2bm2bek3eqcyu4oeyiloy

A New System C-Based Foundation for the CE Curriculum [chapter]

R. Shankar, S. Jayadevappa
2004 Microelectronics Education  
VLSI Design Software Hardware Co-Design Data Structures and Algorithms Computer Architecture OS and RTOS Network Protocol SoC Design  ...  Similarly, software concepts are addressed with courses on data structures and algorithms, operating systems, and software engineering.  ...  The language supports multiple levels of abstraction, a common environment for design and verification, and hardware-software co-design.  ... 
doi:10.1007/978-1-4020-2651-5_7 fatcat:nlw5it54prbljarw6s4z4vlxk4

A transaction-based unified architecture for simulation and emulation

S. Hassoun, M. Kudlugi, D. Pryor, C. Selvidge
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Creating separate verification environments for simulation and emulation slows the design cycle and it requires additional human efforts.  ...  Transactions provide synchronization only as needed and cycle and event-based synchronization common in emulators.  ...  Nayak and S. Arole for help with testcases; D. Scott and M. Naik for the simulation implementation discussions; J. Stickly for cell phone demo and benchmarking; V. Gupta, J. Evans, and A.  ... 
doi:10.1109/tvlsi.2004.840763 fatcat:b7lzaxy2yfcl5oge5sknqiz47e

A TLM-Based Platform to Specify and Verify Component-Based Real-Time Systems

Mostafavi Amjad Davoud, Zolfy Lighvan Mina
2020 Zenodo  
Some of them are very precise but hard to specify complex systems like TRIO, and others do not support object oriented design and hardware/software co-design in real-time systems.  ...  This paper is about modeling and verification languages with their pros and cons. Modeling is dynamic part of system development process before realization.  ...  It provides an essential ESL framework for architecture analysis, software development, software performance analysis, and hardware verification [9] . • With TLM method you can make software and hardware  ... 
doi:10.5281/zenodo.3603849 fatcat:amj3ihbdyfdapecebjq5mwmdvy
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