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FinFETs: From Devices to Architectures

Debajit Bhattacharya, Niraj K. Jha
2014 Advances in Electronics  
We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.  ...  We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs.  ...  Conflict of Interests The authors declare that there is no conflict of interests regarding the publication of this paper. Acknowledgment This work was supported by NSF under Grant nos.  ... 
doi:10.1155/2014/365689 fatcat:wj3mk6blenfwtesg43n5qfevfq

Comprehensive die-level assessment of design rules and layouts

Rani S. Ghaida, Yasmine Badr, Mukul Gupta, Ning Jin, Puneet Gupta
2014 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)  
The framework uses a generated virtual standard-cell library coupled with a mix of physical design, semiempirical, and machine-learning-based models to estimate area and delay at the chip level.  ...  For instance, a study of well-to-active spacing rule reveals a non-monotone dependence of rule value to chip area (although the dependence to cell area is monotone) due to delay changes coming from well-proximity  ...  The fin grid needs to be in accordance with the cell-height so that it is maintained after cell-placement in the design.  ... 
doi:10.1109/aspdac.2014.6742867 dblp:conf/aspdac/GhaidaBGJG14 fatcat:uut26gbydbfyfgxujs7hqdndli

FinFET Circuit Design [chapter]

Prateek Mishra, Anish Muttreja, Niraj K. Jha
2010 Nanoelectronic Circuit Design  
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. FinFETs are double-gate devices.  ...  The two gates of a FinFET can either be shorted for higher perfomance or independently controlled for lower leakage or reduced transistor count. This gives rise to a rich design space.  ...  In this chapter, we explored different kinds of cell libraries that are possible via SG-, LP-, IG-, and IG/LP-mode FinFET logic gates.  ... 
doi:10.1007/978-1-4419-7609-3_2 fatcat:nl33ampqhzdfvkil6gf42tyj3y

Back to the Future: Digital Circuit Design in the FinFET Era

Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, Mircea R. Stan
2017 Journal of Low Power Electronics  
In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes.  ...  As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital  ...  Acknowledgments: This work was supported by NSF grants CCF 1619127 and CCF 1543837, by DARPA under the UPSIDE and PERFECT programs and by the Center for Future Architecture Research (C-FAR), one of six  ... 
doi:10.1166/jolpe.2017.1489 fatcat:b5nc5b3rajb6bf6zmsrtz63tby

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices

Animesh Datta, Ashish Goel, Riza Tamer Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
However, efficient design of large-scale circuits with DG devices is not well explored due to lack of proper modeling and large-scale design simulation tools.  ...  An efficient circuit synthesis methodology comprised of proposed low-power logic options in FinFET design library has been developed.  ...  FinFET-Device-Based Circuit Synthesis Initially, both the standard cell design libraries (i.e., 3-T library and Extended library) are developed and compiled with the Synopsys Library Compiler.  ... 
doi:10.1109/tcad.2007.896320 fatcat:txip2l4fgzg4dnwesim2ym7aim

CMOS logic design with independent-gate FinFETs

Anish Muttreja, Niket Agarwal, Niraj K. Jha
2007 2007 25th International Conference on Computer Design  
Various Fin-FET logic design styles, based on independent control of FinFET gates, are studied. A new low-leakage logic style is presented.  ...  Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits.  ...  FinFET-based standard cell library.  ... 
doi:10.1109/iccd.2007.4601953 dblp:conf/iccd/MuttrejaAJ07 fatcat:legxajdw7ffrxhvtye5fuetwiy

Exploiting Challenges of Sub-20 nm CMOS for Affordable Technology Scaling [article]

Kaushik Vaidyanathan
2015 arXiv   pre-print
and standard cells.  ...  Just continuing to co-optimize leaf cell circuit and layout designs with process technology does not enable us to exploit the challenges of a sub-20 nm CMOS.  ...  Track height is fixed for all cells in a given standard cell library, and our goal is to minimize track height without compromising other goals listed below.  ... 
arXiv:1509.00885v1 fatcat:5mcetdrz2rbhbbtwwf5av36p2a

Many-tier Vertical GAAFET (V-FET) for Ultra-miniaturized Standard Cell Designs Beyond 5 nm

Taigon Song
2020 IEEE Access  
Our study shows that 2-tier V-FET standard cells provide a −35.6% area reduction with a cost of +16.5% wirelength and +13.2% parasitic capacitance increase compared to 1-tier V-FET cells.  ...  We emphasize that the design freedom to place transistors on top of each other and proper interconnect structures lead to ultra-scale miniaturized standard cell designs.  ...  of optimal standard cell design.  ... 
doi:10.1109/access.2020.3015596 fatcat:4e6e3ktvcfc6nkqh7xydbevdwm

Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
FinFET-Device-Based Circuit Synthesis Initially, both the standard cell design libraries (i.e., 3-T library and Extended library) are developed and compiled with the Synopsys Library Compiler.  ...  To explore the benefits of extended sizing options in IG FinFET technology, we have developed two separate libraries. 1) 3-T Library: It consists of different sizing options for 3-T FinFET logic cells.  ...  /FinFET devices, for high-performance logic and memory applications.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky

Soft Error Impact on FinFET and CMOS XOR Logic Gates

Rafael N. M. Oliveira, Cristina Meinhardt
2020 Journal of Integrated Circuits and Systems  
Also, this work explore the nominaland near-threshold operation of these XOR topologies. Resultsshows that FinFET devices are significantly more robust to theradiation effects.  ...  With the advance of computer systems, XORgates design became essential on arithmetic circuits.Atnanometer nodes, despite the electrical characterization, de-signers must to consider soft error impact on  ...  ACKNOWLEDGEMENTS This work was financed in part by National Council for Scientific and Technological Development CNPq and the Propesq/UFSC.  ... 
doi:10.29292/jics.v15i2.131 fatcat:nxkjgwzxf5ht7e7sweyi6256vy

Progress in nanoscale dry processes for fabrication of high-aspect-ratio features: How can we control critical dimension uniformity at the bottom?

Kenji Ishikawa, Kazuhiro Karahashi, Tatsuo Ishijima, Sung Il Cho, Simon Elliott, Dennis Hausmann, Dan Mocuta, Aaron Wilson, Keizo Kinoshita
2018 Japanese Journal of Applied Physics  
Kushner for giving ideas on this review; and Drs. Miyako  ...  The traditional standard-cell based design methodologies rely on a large library of standard cells to synthesize the logic of the design.  ...  Transistor-level scaling At the transistor level, Alioto reported that the cell height affected the layout density in the physical layout design of fin-FET standard cells. 203) The cell height varies  ... 
doi:10.7567/jjap.57.06ja01 fatcat:cjzyhljjzfas5mvaouwvxvlq3q

Design and Analysis of Johnson Counter Using Finfet Technology

Myneni Jahnavi Myneni Jahnavi
2013 IOSR Journal of VLSI and Signal processing  
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits.FinFET, which is a double-gate field effect transistor (DGFET), is more versatile than traditional  ...  Double-gate (DG) FinFETs has better short channel effects performance compared to the conventional CMOS and stimulates technology scaling.  ...  Siva Yellampalli of UTL technologies for their support in the lab, and especially the first author is thankful to the management of Don Bosco Institute of Technology, Bangalore for their constant encouragement  ... 
doi:10.9790/4200-0160106 fatcat:hdbvjkcldbhutardkebeuqei5y

β-Gallium oxide power electronics

Andrew J. Green, James Speck, Grace Xing, Peter Moens, Fredrik Allerstam, Krister Gumaelius, Thomas Neyer, Andrea Arias-Purdue, Vivek Mehrotra, Akito Kuramata, Kohei Sasaki, Shinya Watanabe (+22 others)
2022 APL Materials  
Due to the favorable intrinsic material properties of gallium oxide, namely, critical field strength, widely tunable conductivity, mobility, and melt-based bulk growth, the major targeted application space  ...  Maximizing the potential for a new semiconductor system requires a concerted effort by the community to address technical barriers which limit performance.  ...  The whole design space for AlGaO/β-Ga 2 O 3 heterostructures has not been fully explored.  ... 
doi:10.1063/5.0060327 fatcat:5o63vyzrgjbr3o7dqbh6h3j6wu

Enabling Design of Low-Volume High-Performance ICs

Meric Isgenc
2019
To this end, this dissertation explores opportunities to extend the use of advanced CMOS nodes for low-volume ICs by trading some amount of chip area for a reduction in design complexity, but without significantly  ...  , we designed multiple digital ICs in a commercial 14/16 nm FinFET process.  ...  Since the number of fins is discrete in FinFETs, there is a much restrictive design space for a given logic cell.  ... 
doi:10.1184/r1/8198846.v1 fatcat:w45i6jbi4nhv5cxlykj4ypva6u

MULTI-THRESHOLD LOW POWER-DELAY PRODUCT MEMORY AND DATAPATH COMPONENTS UTILIZING ADVANCED FINFET TECHNOLOGY EMPHASIZING THE RELIABILITY AND ROBUSTNESS

Avinash Yadav
2021
In our study, we explored the ASAP7 library from Arizona State University, developed in collaboration with ARM Holdings.  ...  An exhaustive analysis of the INVx1 delay variation for different operating conditions was also included, to assess the robustness.The 7nm FinFET device was then employed into 6T SRAM cells and 16 function  ...  This helps to produce equal height standard cells. SRAM cells have different design rules and follow the same fin pitch in the entire layout [18] .  ... 
doi:10.25394/pgs.13335494.v1 fatcat:4zmkhntx3vbwnpjakdjws4kys4
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