Filters








14,697 Hits in 4.9 sec

Design issues and tradeoffs for write buffers

K. Skadron, D.W. Clark
Proceedings Third International Symposium on High-Performance Computer Architecture  
We address some performance issues that arise in the design of processor write buffers.  ...  Good write buffer designs achieve a balance between these functions. This paper considers write buffer designs for systems with at least two levels of cache.  ...  We also thank the referees for their suggestions.  ... 
doi:10.1109/hpca.1997.569650 dblp:conf/hpca/SkadronC97 fatcat:emcuajahwjcd5du2zxddtytcza

Architectural and organizational tradeoffs in the design of the MultiTitan CPU

N. P. Jouppi
1989 SIGARCH Computer Architecture News  
We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with  ...  Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals.  ...  A write-through cache requires a write buffer and its associated control logic if good performance is to be maintained, while a write-back cache does not need a write buffer. • A write-back cache generates  ... 
doi:10.1145/74926.74957 fatcat:cib7kgqhyncyvaku3b6hsbdd6y

Architectural and organizational tradeoffs in the design of the MultiTitan CPU

N. P. Jouppi
1989 Proceedings of the 16th annual international symposium on Computer architecture - ISCA '89  
We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with  ...  Researchers at WRL cooperate closely and move freely among the various levels of system design. This allows us to explore a wide range of tradeoffs to meet system goals.  ...  A write-through cache requires a write buffer and its associated control logic if good performance is to be maintained, while a write-back cache does not need a write buffer. • A write-back cache generates  ... 
doi:10.1145/74925.74957 dblp:conf/isca/Jouppi89 fatcat:3kobxt37tfdg7igbosjwt6pnxy

Energy-security tradeoff in a secure cache architecture against buffer overflow attacks

Koji Inoue
2005 SIGARCH Computer Architecture News  
The number and the placement policy of the replica line strongly affect both energy and vulnerability.  ...  In this paper, we propose a cache architecture, called SCache, to detect buffer-overflow attacks at run time. Furthermore, the energy-security efficiency of SCache is discussed.  ...  This means that there is a tradeoff between energy and security, thus it is very important to explore the design space for coping both high security and low energy consumption.  ... 
doi:10.1145/1055626.1055638 fatcat:hzduuk6bnzezhivcaw7scut6eu

Supporting efficient noncontiguous access in PVFS over Infiniband

Jiseheng Wu, Wyckoff, Panda
2003 Proceedings IEEE International Conference on Cluster Computing CLUSTR-03  
We have designed and incorporated this approach in a version of PVFS over InfiniBand.  ...  We propose a novel approach, RDMA Gather/Scatter, to transfer noncontiguous data for such I/O accesses.  ...  We are also thankful to Jiuxing Liu and Pavan Balaji for discussion with us.  ... 
doi:10.1109/clustr.2003.1253333 dblp:conf/cluster/WuWP03 fatcat:zesr2ucmyban7e3fmo6jegahqy

IBM Database 2 performance: Design, implementation, and tuning

J. M. Cheng, C. R. Loosley, A. Shibamiya, P. S. Worthington
1984 IBM Systems Journal  
The Buffer Manager algorithms for reassigning and writing a buffer are complex.  ...  Performance-related internal design tradeoffs Numerous performance-related tradeoffs were made during the design and development phases of Dp2, with the goal of providing the best overall product for the  ... 
doi:10.1147/sj.232.0189 fatcat:qb33v5a5u5e6rmjhpxmnam7n2a

A Versatile Performance and Energy Simulation Tool for Composite GPU Global Memory

Bin Wang, Yizheng Jiao, Weikuan Yu, Xipeng Shen, Dong Li, Jeffrey S. Vetter
2013 2013 IEEE 21st International Symposium on Modelling, Analysis and Simulation of Computer and Telecommunication Systems  
It can enable further research on the design of GPU global memory for performance and energy tradeoffs. 1526-7539/13 $26.00  ...  reveal hardware organization of both GPU compute units and its memory system.  ...  We are very thankful for GPU equipment donated from NVIDIA to Auburn University.  ... 
doi:10.1109/mascots.2013.39 dblp:conf/mascots/WangJYSLV13 fatcat:muvotcf4k5gzvhu74apdomtvh4

When data management systems meet approximate hardware

Bingsheng He
2014 Proceedings of the VLDB Endowment  
In this vision paper, we sketch the initial design of ApproxiDB, discuss the technical challenges in building this system and outline an agenda for future research.  ...  We propose a DBMS ApproxiDB with its design, implementation and optimization aware of the underlying approximate hardware.  ...  Acknowledgement The author would like to thank Yinan Li, Qiong Luo, Saurabh Jha, Mian Lu and anonymous reviewers for their insightful comments.  ... 
doi:10.14778/2732951.2732961 fatcat:fvs5u3mgt5bkxp5nlbzcu7257i

Exploiting Cross-Layer Hotness Identification to Improve Flash Memory System Performance [chapter]

Jinhua Cui, Weiguo Wu, Shiqiang Nie, Jianhang Huang, Zhuang Hu, Nianjun Zou, Yinfeng Wang
2016 Lecture Notes in Computer Science  
Then, based on the hotness information provided by buffer management, the threshold voltages of a cell for write-hot data are decreased for wearing reduction, while these for read-hot data are increased  ...  In this paper, the access hotness characteristics are exploited for read performance and endurance improvement.  ...  Acknowledgment The authors would like to thank the anonymous reviewers for their detailed and thoughtful feedback which improved the quality of this paper significantly.  ... 
doi:10.1007/978-3-319-47099-3_2 fatcat:54kb7qklrzdt7dx3e3mkvru3sq

A case for small row buffers in non-volatile main memories

Justin Meza, Jing Li, Onur Mutlu
2012 2012 IEEE 30th International Conference on Computer Design (ICCD)  
area penalty and/or design complexity.  ...  Emerging non-volatile memories (NVMs) such as PCM, STT-RAM, and RRAM, however, do not have destructive read operations, opening up opportunities for employing small row buffers without incurring additional  ...  [4] employed multiple, narrow rows in a PCM main memory for reducing array reads and writes, it focused on (1) a traditional DRAM data path design, (2) an isoarea reorganization, requiring more area overhead  ... 
doi:10.1109/iccd.2012.6378685 dblp:conf/iccd/MezaLM12 fatcat:mngr2k32ljblbigki7f3wynw4m

Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
2005 IEEE Transactions on Signal Processing  
The implementation issues of the internal buffer are also discussed, and some real-life experiments are given to show that the area and power for the internal buffer are highly related to memory technology  ...  As for the 2-D DWT, the large amount of the frame memory access and the die area occupied by the embedded internal buffer become the most critical issues.  ...  The design tradeoff mainly comes from the frame memory access bandwidth and the internal buffer size. In [8] , the design alternatives are evaluated in the aspects of power and memory requirements.  ... 
doi:10.1109/tsp.2005.843704 fatcat:4jtnw4t73vg6xltq47ltrajjqy

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Kiryong Kim, Seong-Ook Jung
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full V DD , without the need for the boosted WL  ...  The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme.  ...  It should be noted that the proposed differential SRAM architecture can resolve the half-select issue without the need for a write-back scheme, and it exhibits a competitive area; it also exhibits a full-swing  ... 
doi:10.1109/tvlsi.2015.2450500 fatcat:med52kr64bau3cdh6xe452djde

Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)

Wei Xu, Hongbin Sun, Xiaobin Wang, Yiran Chen, Tong Zhang
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Due to unique operational characteristics of its storage device magnetic tunneling junction (MTJ), STT RAM is inherently subject to a write latency versus read latency tradeoff that is determined by the  ...  to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors.  ...  is full, and we always try to empty the write buffer during idle cycles.  ... 
doi:10.1109/tvlsi.2009.2035509 fatcat:m2envln64zbx5eraha3wwpovwu

A comparison of Flashcache with IQ-Twemcached

Yazeed Alabdulkarim, Marwan Almaymoni, Ziwen Cao, Shahram Ghandeharizadeh, Hieu Nguyen, Lingnan Song
2016 2016 IEEE 32nd International Conference on Data Engineering Workshops (ICDEW)  
Using Facebook's Flashcache as the representative of HsC and IQ-Twemcached as the representative of AsC, this study quantifies their tradeoffs using both a read-heavy and a write-heavy workload.  ...  Person-to-person cloud service providers such as Facebook use Host-side (HsC) and Application-side (AsC) caches to enhance performance.  ...  Our evaluation quantifies their tradeoffs for both read-heavy and write-heavy workloads.  ... 
doi:10.1109/icdew.2016.7495610 dblp:conf/icde/AlabdulkarimACG16 fatcat:swkspv6tizf6hp6zxjdlic6wj4

PVS-NoC: Partial Virtual Channel Sharing NoC Architecture

Khalid Latif, Amir-Mohammad Rahmani, Liang Guang, Tiberiu Seceleanu, Hannu Tenhunen
2011 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing  
A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented.  ...  We propose sharing the VC buffers among dual inputs, which provides the performance advantage as conventional VC-based router with minimized overhead.  ...  ACKNOWLEDGEMENTS This work is supported by the Nokia Foundation and DOMES project (123518/2008) funded by the Academy of Finland.  ... 
doi:10.1109/pdp.2011.87 dblp:conf/pdp/LatifRGST11 fatcat:bidmk24qxbbudmjrnzd73flwuy
« Previous Showing results 1 — 15 out of 14,697 results