1,395 Hits in 4.5 sec

Semiconductor Rams - a Status Report

G.E. Moore
1971 Computer  
Very simple structures can-be employed for these bits w tion of med-ium or large bipolar random access memories.  ...  Figure 4 -A 2K x 18 bipolar memory complete with data and address registers for operation at a cycle time of 120 ns. This memory utilizes 256 bit bipolar memory arrays.  ... 
doi:10.1109/c-m.1971.216765 fatcat:t5tofnco7vetfi76hl3f3vagiy

Power/area analysis and optimization of a DS-SS receiver for an integrated sensor microsystem

N. Aydin, T. Arslan, D.R.S. Cumming
2003 Euromicro Symposium on Digital System Design, 2003. Proceedings.  
When considering the design of telecommunication system for such a network, the receiver is the key performance critical block.  ...  We demonstrate that up to 59% and 11% savings in area and power respectively could be achieved by optimizing input data size and internal register width for a particular application while maintaining signal  ...  of 128, and 9 bits with a PN code length of 256.  ... 
doi:10.1109/dsd.2003.1231973 dblp:conf/dsd/AydinAC03 fatcat:icrxq5pktnh4tbshkp7h7ofxee

Introduction to Advanced Semiconductor Memories [chapter]

2009 Advanced Semiconductor Memories  
Special memories are also available such as nonvolatile random access memory (NOVRAM) or shadow RAM configurations that combine on the same chip, a SRAM array, and a backup EEPROM array of equal bits.  ...  A holographic random access memory (HRAM) design has been proposed that can lead to the implementation of compact and inexpensive modules that can be used to construct large read-write memories.  ... 
doi:10.1109/9780470544136.ch1 fatcat:5agoaobfx5aqfmmsnmsj4a4mwy

Semiconductor Memories

H. Virani
1998 Active and Passive Electronic Components  
CLASSIFICATION OF MEMORIES All the memories to be discussed are Random Access Memories in the sense that any location can be accessed at random taking the same time as any other location.  ...  . 6 RANDOM ACCESS MEMORIES (OR READ/WRITE MEMORIES) These consist of a matrix of memory cells, bistable elements arranged in x rows and y columns.  ... 
doi:10.1155/1998/18137 fatcat:6rvjngof5vcmbeb6bsmwl6okhu

Single-Readout High-Density Memristor Crossbar

M. A. Zidan, H. Omran, R. Naous, A. Sultan, H. A. H. Fahmy, W. D. Lu, K. N. Salama
2016 Scientific Reports  
The proposed methods require a single memory access per pixel for an array readout.  ...  Data stored in a memory array is naturally random 28 , which leads  ...  For the memristor device, we adopted a bipolar device model proposed for memory operations 5 .  ... 
doi:10.1038/srep18863 pmid:26738564 pmcid:PMC4703991 fatcat:73cmjfegpfgzxayhkujuvlxlc4

50 & 25 Years Ago

2021 Computer  
Design Considerations for a Bipolar 256 bit Random Access Memory; Jerry Gray (p. 18) "The increasing use of computers and peripherals with higher speed capabilities generated a demand for a low cost, low  ...  Deign Considerations for Semiconductor Random Access Memory Systems; Bernard A.  ... 
doi:10.1109/mc.2021.3049790 fatcat:ud74t5xwjzacdljuvjeybghbsi

A cost/performance analysis of integrated-circuit core memories

Dana W. Moore
1966 Proceedings of the November 7-10, 1966, fall joint computer conference on XX - AFIPS '66 (Fall)  
Those chosen are applicable to random-access ferrite-core memories, and each design makes use of integrated circuitry to the extent permitted by the devices which presently may be procured in volume quantities  ...  Consequently, when capacity requirements are large (> 10 6 bits), it is sometimes practical to institute a dollar-speed tradeoff to fill the void between rotating machinery and high-speed, random-access  ... 
doi:10.1145/1464291.1464321 dblp:conf/afips/Moore66 fatcat:hhz5dout4nddxgqewha4yg5sgm

A Parallel Radix-4 Fast Fourier Transform Computer

M.J. Corinthios, K.C. Smith, J.L. Yen
1975 IEEE transactions on computers  
The organization and design of a radix-4 256-word synchronous sequential FFT signal processor which has been constructed and which performs real-time processing of signals sampled at a rate of up to 1.6  ...  System considerations for reducing roundoff errors and for performing other processes based on the Fourier transform are discussed.  ...  Bipolar random access memories are used in implementing the input buffer memory circuitry, and bipolar programmable read only memories (PROM's) are used as the storage medium for the weighting coefficients  ... 
doi:10.1109/t-c.1975.224085 fatcat:r4tloiid2rbeffn2qy6pmcu4da

ILLIAC II-A Short Description and Annotated Bibliography

H. C. Brearley
1965 IEEE Transactions on Electronic Computers  
Order fetches from the main 1.8 -J,LS. core memory are minimized by packing two to four orders per word, and by holding two words of orders in the flow gating memory for execution of short loops.  ...  The bibliography lists 40 papers related to the design of this computer.  ...  Gaps between the blocks allow for head switching so that following any block transfer, random access to one of the 16 blocks in the next sector may be obtained without waiting.  ... 
doi:10.1109/pgec.1965.264146 fatcat:otinz5xokrfsdeolao7tpqhr2e

Bipolar Morphological Neural Networks: Gate-Efficient Architecture for Computer Vision

Elena E. Limonova, Daniil M. Alfonso, Dmitry P. Nikolaev, Vladimir V. Arlazarov
2021 IEEE Access  
consideration.  ...  We have recently proposed a bipolar morphological network as a hardware-oriented model for these computer types, the computationally intensive parts of which use only maximum and addition.  ...  The memory is called random-access because it has the same time to access a word for all words.  ... 
doi:10.1109/access.2021.3094484 fatcat:zu6d4mfze5elpcrqga4swrlmgm

Hardware-Efficient On-line Learning through Pipelined Truncated-Error Backpropagation in Binary-State Networks

Hesham Mostafa, Bruno Pedroni, Sadique Sheik, Gert Cauwenberghs
2017 Frontiers in Neuroscience  
In this paper, we describe a hardware-efficient on-line learning technique for feedforward multi-layer ANNs that is based on pipelined backpropagation.  ...  By using binary state variables in the feedforward network and ternary errors in truncated-error backpropagation, the need for any multiplications in the forward and backward passes is removed, and memory  ...  Foundation Early Postdoc Mobility fellowship P2ZHP2_164960, by Fujitsu Labs of America, by Intel Corporation, and by the National Science Foundation and the Nanoelectronics Research Corporation (NERC), a  ... 
doi:10.3389/fnins.2017.00496 pmid:28932180 pmcid:PMC5592276 fatcat:erdw4ywtuvda3o7lrgohggfwm4

A production implementation of an associative array processor

Jack A. Rudolph
1972 Proceedings of the December 5-7, 1972, fall joint computer conference, part I on - AFIPS '72 (Fall, part I)  
Each array consists of 65,536 bits organized as a multi-dimensional access memory matrix of 256 words * T. M.  ...  Goodyear Aerospace Corporation, Akron, Ohio by 256 bits with parallel access to up to 256 bits at a time in either the word or bit direction.  ... 
doi:10.1145/1479992.1480023 dblp:conf/afips/Rudolph72 fatcat:ju2lqal7ozg5xccdqypjzj7ezq

Hardware-efficient on-line learning through pipelined truncated-error backpropagation in binary-state networks [article]

Hesham Mostafa, Bruno Pedroni, Sadique Sheik, Gert Cauwenberghs
2017 arXiv   pre-print
In this paper, we describe a hardware-efficient on-line learning technique for feedforward multi-layer ANNs that is based on pipelined backpropagation.  ...  By using binary state variables in the feedforward network and ternary errors in truncated-error backpropagation, the need for any multiplications in the forward and backward passes is removed, and memory  ...  Each core uses 256 × 49 = 12,544 bits of internal memory to store the states of the 256 neurons. A Pseudo Random Number Generator (PRNG) supplies the dropout signal to the core.  ... 
arXiv:1707.03049v2 fatcat:d2cjco6znnbk3cfrw3upeoxaku

Generating complex waveforms

Richard V. Wolf, Robert C. Bilger
1972 Behavior Research Methods  
We have built a device, incorporating solid state memory, that can store, time, and transfer previously computed digital values, so that a computer is no longer necessary to generate the waveforms.  ...  Specifications of the digital-to-analog converter and appropriate settings of the filter are discussed, along with a simplified procedure for calculating waveforms that have line spectra.  ...  We selected an MOS, random access device, organized as a 256-by I-bit chip (INTEL nOlA), each chip corresponding to 1 bit of a 15-bit memory word (see Fig. 4 ).  ... 
doi:10.3758/bf03210008 fatcat:jjztdp74ifdhlmodyggng2cvma

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim
2021 IEEE Open Journal of Circuits and Systems  
Resistive random access memory (ReRAM)-based computing in-memory (CIM) is a promising solution to overcome the von-Neumann bottleneck in conventional computing architectures.  ...  The proposed 4T2R cell occupies a smaller area than prior SRAMbased CIM bit-cells. A 128 × 128 ReRAM macro is designed in 40nm CMOS technology.  ...  Fig. 2 (c) shows an example I-V curve for a bipolar HfOx-based ReRAM device [16] .  ... 
doi:10.1109/ojcas.2020.3042550 fatcat:murlufzvg5bdppggz644mpf3pm
« Previous Showing results 1 — 15 out of 1,395 results