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Oral Sessions

2021 2021 18th International SoC Design Conference (ISOCC)  
RF1-2 (128) Design of Multiplying Delay Locked Loop that prevents Harmonic Lock and is insensitive to PVT Variation 14:45-15:00  ...  First, the SRAM-based Computing-in-Memory (CIM) chips has demonstrated high performance and high energyefficient, including topic "Design Methodology towards High-Precision SRAM based Computation-in-Memory  ...  for AI Edge Devices" and "Energy-efficient CIM SoC design for edge AI devices".  ... 
doi:10.1109/isocc53507.2021.9613992 fatcat:hhfkmbvkxnd2xe24mztt4lzl3i

Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications [article]

Vivek Parmar, Syed Shakib Sarwar, Ziyun Li, Hsien-Hsin S. Lee, Barbara De Salvo, Manan Suri
2022 arXiv   pre-print
Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse.  ...  We found that significant energy benefits (>=80%) can be achieved for hand detection (IPS=40) and eye segmentation (IPS=6) by introducing non-volatile memory in the memory hierarchy for designs at 7nm  ...  We propose two strategies, P0 and P1 mappings shown in Fig. 5(c ), to adopt NVM-based pipelines in the edge devices for the XR-AI workloads.  ... 
arXiv:2206.06780v1 fatcat:yy6zrxginrc7jozpid4yhr3hfq

Guest Editorial: IEEE TC Special Issue On Smart Edge Computing and IoT

Luca Benini, Simone Benatti, Taekwang Jang, Abbas Rahimi
2021 IEEE transactions on computers  
Ç T HE evolution of the Internet of Things (IoT) is changing the nature of edge-computing devices.  ...  For this reason, both architectural optimizations and neural network performance tuning and analysis tools are important tools for the evolution of next generation edge devices.  ...  The paper entitled "Design and Simulation of a Hybrid Architecture for Edge Computing in 5G and Beyond" by Rahimi et al. explores computing techniques and architectural frameworks for Edge Computing in  ... 
doi:10.1109/tc.2021.3082675 fatcat:ffx3cnnozbbivf5zokiil62irq

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Liang Chang, Chenglong Li, Zhaomin Zhang, Jianbiao Xiao, Qingsong Liu, Zhen Zhu, Weihang Li, Zixuan Zhu, Siqi Yang, Jun Zhou
2021 Science China Information Sciences  
In addition, we introduce the story of CIM and implementation methodologies of CIM architecture.  ...  However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture.  ...  [77] designed a CIM macro based on 12T SRAM that can perform XNOR operations for binary networks. In 2020, Si et al.  ... 
doi:10.1007/s11432-021-3234-0 fatcat:np7wtg24rzavbc5fsmammikn3i

Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework [article]

Muhammad Shafique, Alberto Marchisio, Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif
2021 arXiv   pre-print
Towards the end, we discuss how these techniques can be combined in an integrated cross-layer framework for realizing robust and energy-efficient Edge AI systems.  ...  Deploying advanced Neural Networks (NN), such as deep neural networks (DNNs) and spiking neural networks (SNNs), that offer state-of-the-art results on resource-constrained edge devices is challenging  ...  ACKNOWLEDGMENTS This work was partly supported by Intel Corporation through Gift funding for the project "Cost-Effective Dependability for Deep Neural Networks and Spiking Neural Networks".  ... 
arXiv:2109.09829v1 fatcat:rfbshpbaevgxdi4mnjskis5lty

Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing Errors

Pramesh Pandey, Noel Daniel Gundi, Prabal Basu, Tahmoures Shabanian, Mitchell Craig Patrick, Koushik Chakraborty, Sanghamitra Roy
2020 Journal of Low Power Electronics and Applications  
AI evolution is accelerating and Deep Neural Network (DNN) inference accelerators are at the forefront of ad hoc architectures that are evolving to support the immense throughput required for AI computation  ...  In this paper, we dive deep into DNN architecture to uncover some unique challenges and opportunities for operation in the NTC paradigm.  ...  Section 3.2 presents the challenges in the detection and handling of timing errors in high performance environment essential for a high throughput NTC system.  ... 
doi:10.3390/jlpea10040033 fatcat:ngmamcqqpngxdmhpxuttgn5ena

Computing Nearer to Data

Thomas M. Coughlin, William R. Tonti
2022 Computer  
Constraints on the capability and performance of CPU-based processing have resulted in new approaches for the design of computing systems that may cost-effectively meet the growing demand for processing  ...  In-memory computing performs certain computation tasks by exploiting the physical attributes of memory devices, which can be charged-based or resistance-based devices, as shown in Figure 2 .  ...  Computing in Science & Engineering (CiSE) is a cross-disciplinary, international publication that meets this need by presenting contributions of high interest and educational value from a variety of fields  ... 
doi:10.1109/mc.2022.3171354 fatcat:qnmg3qufnvfahjbe6jzqxrhzyy

TinyML: Enabling of Inference Deep Learning Models on Ultra-Low-Power IoT Edge Devices for AI Applications

Norah N. Alajlan, Dina M. Ibrahim
2022 Micromachines  
In addition, connecting IoT devices to the cloud to transfer raw data and perform processing causes delayed system responses, exposes private data and increases communication costs.  ...  Many of these devices are based on machine learning (ML) models, which render them intelligent and able to make decisions.  ...  This leads to a rise in the volume of data generated that in turn needs high computing performance and large amounts of storage space.  ... 
doi:10.3390/mi13060851 pmid:35744466 pmcid:PMC9227753 fatcat:hnog2bwiojflrafok4ek2ecjy4

EMC2-NIPS 2019 Abstracts of Invited Talks

2019 2019 Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing - NeurIPS Edition (EMC2-NIPS)  
In this talk, we will describe how joint algorithm and hardware design can be used to reduce energy consumption while delivering real-time and robust performance for applications including deep learning  ...  This talk will uncover the need for building accurate, platform-specific power and latency models for convolutional neural networks (CNNs) and efficient hardware-aware CNN design methodologies, thus allowing  ...  The applications include precision farming, health care monitoring, and edge-based surveillance. xi Advances and Prospects for In-memory Computing Naveen Verma, Princeton University Edge AI applications  ... 
doi:10.1109/emc2-nips53020.2019.00007 fatcat:bvtcsgwxsrh3bmwh6tba3ly3ra

Proof-of-PUF Enabled Blockchain: Concurrent Data and Device Security for Internet-of-Energy

Rameez Asif, Kinan Ghanem, James Irvine
2020 Sensors  
In addition to this, we review the key areas of design, development, and implementation, which will give us the insight on seamless integration with legacy IoE systems, reliability, cyber resilience, and  ...  This hybrid approach, hereinafter termed as PUFChain, provides device and data provenance which records data origins, history of data generation and processing, and clone-proof device identification and  ...  ) and use-cases in the energy utilities.  ... 
doi:10.3390/s21010028 pmid:33374599 pmcid:PMC7793093 fatcat:h2b4djvqojdehjxrku4nkjl2dq

F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors

SukHwan Lim, Yong Pan Liu, Luca Benini, Tanay Karnik, Hsie-Chia Chang
2021 2021 IEEE International Solid- State Circuits Conference (ISSCC)  
Therefore, an edge neural processing chip with simultaneous low power, high performance, and low cost is in urgent need for the fast-growing AI-and-IoT (AIoT) market.  ...  His research interests include soft-error resilience, energy-efficient digital design, low-voltage static random-access memory (SRAM) design, machine learning accelerators, productive design methodologies  ...  Following technology advances in high-performance computation systems and fast growth of data acquisition, machine learning, and especially deep neural networks (DNNs), made remarkable success in many  ... 
doi:10.1109/isscc42613.2021.9365804 fatcat:6qgx72c6bjcgndua43f4fsdggm

Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems

Priyadarshini Panda, Kaushik Roy
2020 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)  
Priya's research interests lie in Neuromorphic Computing: spanning energy-efficient design methodologies for deep learning networks, novel supervised/unsupervised learning algorithms for spiking neural  ...  Hence, we need fundamentally new approaches to sustain exponential growth in performance at high energy-efficiency beyond the end of the CMOS roadmap in the era of 'data deluge' and emergent data-centric  ...  ), for both the embedded and high-performance computing domains.  ... 
doi:10.1109/vlsid49098.2020.00017 dblp:conf/vlsid/Panda020 fatcat:tvsoqomvynaxtkry62vhni4ura

Blood Glucose Prediction in Type 1 Diabetes Using Deep Learning on the Edge

Taiyu Zhu, Lei Kuang, Kezhi Li, Junming Zeng, Pau Herrero, Pantelis Georgiou
2021 2021 IEEE International Symposium on Circuits and Systems (ISCAS)  
In particular, the proposed method achieves an average root mean square error of 19.10 ± 2.04 for a 30-minute prediction horizon (PH) and 32.61 ± 3.45 for a 60-minute PH with high clinical accuracy.  ...  The presented system has the potential to be implemented in wearable medical devices for diabetes care (CGM and insulin pumps) and to be integrated within an Internet of Things platform.  ...  This research has been funded by Engineering and Physical Sciences Research Council (EPSRC EP/P00993X/1) and the President's PhD Scholarship at Imperial College London (UK).  ... 
doi:10.1109/iscas51556.2021.9401083 fatcat:hz7okbfh25e3vmwtvgmy5zbfl4

Table of Contents

2020 2020 International SoC Design Conference (ISOCC)  
In this talk, I will briefly describe the challenges of datacenter infrastructure with the case of Microsoft Catapult and review the latest AI accelerators for cloud datacenters.  ...  Machine learning (ML) and artificial intelligence (AI) technology are revolutionizing many fields of study in computer science as well as a wide range of industry sectors such as information technology  ...  From 1996 to 2003, he was with Samsung Electronics, Korea, involved in SRAM Design Team. He designed various kinds of high-speed SRAM for external cache and buffer memory.  ... 
doi:10.1109/isocc50952.2020.9333052 fatcat:6ij6ahesdzhzphaff6wnwgg7wq

FASTHash: FPGA-Based High Throughput Parallel Hash Table [chapter]

Yang Yang, Sanmukh R. Kuppannagari, Ajitesh Srivastava, Rajgopal Kannan, Viktor K. Prasanna
2020 Lecture Notes in Computer Science  
It is a key component in AI applications which rely on building a model of the environment using observations and performing lookups on the model for newer observations.  ...  We customize our design to implement both static and dynamic hash tables on state-of-the-art FPGA devices.  ...  This work has been supported by Xilinx and by the U.S. National Science Foundation (NSF) under grants OAC-1911229 and SPX-1919289.  ... 
doi:10.1007/978-3-030-50743-5_1 fatcat:ft45zkcbb5bz5gcfj4nnob5ka4
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