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Describing instruction set processors using nML
Proceedings the European Design and Test Conference. ED&TC 1995
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We introduce the formalism nML which is especially suited to describe such processors in terms of their instruction set, an nML description is directly related to the standard description as found in the ...
The philosophy of nML is already applied in two approaches to retargetable code generation and instruction set simulation. ...
Breaking Down the Instruction Set When describing an instruction set, a top-down approach i s a d v ocated. In nML, a hierarchical structure can be imposed onto the instruction set description. ...
doi:10.1109/edtc.1995.470354
dblp:conf/date/FauthPF95
fatcat:rgkbnosi6nex7h5tfh3e2ek64i
Processor modeling for hardware software codesign
1999
Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)
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As a part of this work, we implemented an instruction set simulator generator which takes Sim-nML description of the processor as input and produces C++ code for performance simulator. ...
We envisage the use of the generated simulator for cycle based analysis of the processor and for performance estimation of the system. This work is primarily an extension of nML[2] language. ...
nML nML [2] is a formalism targeted for describing arbitrary single processor computer architecture. nML works at instruction set level and hides the implementation details. ...
doi:10.1109/icvd.1999.745137
dblp:conf/vlsid/RajeshM99
fatcat:siop6p3u6fhqtnqfdis2z4slgu
Generation of software tools from processor descriptions for hardware/software codesign
1997
Proceedings of the 34th annual conference on Design automation conference - DAC '97
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The processor instruction set was described using a language called nML. The TMS320C50 DSP processor and the ARM7 microprocessor were modeled in nML. ...
The resulting instruction set models execute about 25,000 instructions per second, and compiled instruction set simulation models execute about 150,000 instructions per second. ...
Acknowledgments We would like to thank Markus Freericks of the Technical University of Berlin for permission to use the nML language. ...
doi:10.1145/266021.266110
dblp:conf/dac/HartoogRRDDHK97
fatcat:p4kwipkre5bkbo2mvcgheepgtu
Retargetable Program Profiling Using High Level Processor Models
[chapter]
2001
Lecture Notes in Computer Science
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The retargetability makes the profiling tool independent of the target instruction set. ...
We have implemented a retargetable simulation driven code profiler from a high-level processor description language, Sim-nML. ...
Firstly, we have used a retargetable functional simulator generated from a high-level processor description language, Sim-nML. ...
doi:10.1007/3-540-45307-5_20
fatcat:r2baowzak5fmnc5kxbooaee7aq
Architecture Description Languages
[chapter]
2007
Customizable Embedded Processors
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Modeling plays a central role in design automation of embedded processors. ...
The language should be powerful enough to capture high-level description of the processor architectures. ...
ISDL is mainly targeted towards VLIW processors. Similar to nML, ISDL primarily describes the instruction-set of processor architectures. ...
doi:10.1016/b978-012369526-0/50005-x
fatcat:rbib63vmazbs3jpezammkjetxm
Processor Modeling and Design Tools
[chapter]
2006
Industrial Information Technology
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The processor is modeled using a specification language such as Architecture Description Language (ADL). ...
The goal is to find the best possible processor architecture for the given set of application programs under various design constraints such as cost, area, power and performance. ...
ISDL is mainly targeted towards VLIW processors. Similar to nML, ISDL primarily describes the instruction-set of processor architectures. ...
doi:10.1201/9781420007947.ch8
fatcat:azirpu6yajf2dkvpiiqhecdise
Architecture description languages for programmable embedded systems
2005
IEE Proceedings - Computers and digital Techniques
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The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures. ...
Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance. ...
ISDL is mainly targeted towards VLIW processors. Similar to nML, ISDL primarily describes the instruction set of processor architectures. ...
doi:10.1049/ip-cdt:20045071
fatcat:sznyga75n5hk3pongpmyrmffgq
Formal Architecture Specification for Time Analysis
[chapter]
2014
Lecture Notes in Computer Science
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First, we enhance the existing language Sim-nML for describing processors at the instruction level in order to capture modern architecture aspects. ...
Second, we propose a light DSL in order to describe, in a formal prose, architectural aspects related to both the structural aspects as well as to the behavioral aspects. ...
We have drawn a comparison between currently used description languages and formalism. In this paper we have used a processor model that possess real word processor features to test our approach. ...
doi:10.1007/978-3-319-04891-8_9
fatcat:lna4obnk3nhljozkhgazp53pym
Hardware architecture specification and constraint-based WCET computation
2013
2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES)
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OTAWA, a tool providing WCET computation, uses the Sim-nML language to describe the instruction set and XML files to describe the microarchitecture. ...
In this paper, we propose to extend Sim-nML in order to support the description of modern microarchitecture features along the instruction set description and to seamlessly derive the time calculation. ...
Behavior-centric ADLs like ISDL [14] and nML [9] describes the processor by its instruction set architecture. ...
doi:10.1109/sies.2013.6601499
dblp:conf/sies/HerbegueCFR13
fatcat:tb5tewfmdfd3vfg2gz7d56ywza
Automated generation of DSP program development tools using a machine description formalism
1993
IEEE International Conference on Acoustics Speech and Signal Processing
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The machine description need not explicitly list every possible instruction in full length. Instead, a derivation tree is described. ...
The primary goal of our work is to quickly provide system architects with the set of tools necessary for program development (assemblers, instruction set simulators, debuggers and compilers); in particular ...
The abstraction level that nML aims at is the programmer's model of the processor, i.e., the instruction set and the memory model. ...
doi:10.1109/icassp.1993.319154
dblp:conf/icassp/FauthK93
fatcat:ypjlhsa5xrfujkp75fhtswfype
Combining ACSL Specifications and Machine Code
Совмещение ACSL спецификаций с машинным кодом
2018
Proceedings of the Institute for System Programming of RAS
Совмещение ACSL спецификаций с машинным кодом
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The essence of the approach is to build models, both machine code and its specifications in a single logical language, and use target processor ABI to bind machine registers with the parameters of the ...
Such measures include the use of a register type in the highlevel specifications and the translation of the pre-and postconditions into the abstract predicates. ...
The use of the methods and approaches described in this paper will allow you to fully automate deductive verification of machine code without loops for compliance with the contract specification in ACSL ...
doi:10.15514/ispras-2018-30(4)-6
fatcat:nlz6gyfgpnd4pb6vomixlamzle
Development of the Retargetable Tool Suite for Embedded Software
2008
2008 Advanced Software Engineering and Its Applications
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design and implements the Retargetable Tool Suite for Embedded Software(RTS-ES) composed of target code generator, low power/energy optimizer, system simulator and debugger through the proposed Embedded Processor ...
In nML, the processor's IS is described as an attributed grammar with the derivations reflecting the set of legal instructions. nML has been used by the retargetable code generation environment CHESS ...
Operation section describes the Instruction Set(IS) of the processor and organized into various operation groups. ...
doi:10.1109/asea.2008.10
fatcat:tbvpbmlbuzgp5bxu3aokwkfhii
Validating Static WCET Analysis: A Method and Its Application
2019
Worst-Case Execution Time Analysis
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ACM Subject Classification Computer systems organization → Real-time systems Keywords and phrases validation of WCET tools, ISS, nML ...
We hereby show how we have validated the version of the data flow static analyser of OTAWA applied to the AURIX TC275 target processor. ...
Background This section introduces the OTAWA framework used to develop WCET static analysers, and the Sim-NML language used to describe ISA (Instruction Set Architectures). ...
doi:10.4230/oasics.wcet.2019.6
dblp:conf/wcet/SunJC19
fatcat:p6a2fcy5ajc6favczckj44xr4u
A unifying formalism to support automated synthesis of SBSTs for embedded caches
2011
2011 9th East-West Design & Test Symposium (EWDTS)
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Since the related synthesis tool is multi-platform, the Instruction Set Architecture of the target processor must be properly described, as well. ...
and instruction cache memories. ...
Section IV describes the methodology of the processor instruction set definition, based the nML formalism [11] . Section V eventually concludes the paper.
II. ...
doi:10.1109/ewdts.2011.6116421
dblp:conf/ewdts/CarloGIRP11
fatcat:ksvmrzzztbfqvirrrt2g3avmzy
Architecture Description Languages for Retargetable Compilation
[chapter]
2007
The Compiler Design Handbook
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The second and possibly more important need for this is in the design space exploration for the architecture and micro-architecture of the processor being developed. ...
The instruction set description of nML utilizes attribute grammars. ...
A typical behavioral ADL description is close in form to an instruction set reference manual.
nML nML is a simple and elegant formalism for instruction set modeling. ...
doi:10.1201/9781420043839.ch16
fatcat:6uszortfbzadpiu47wqepfz3p4
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